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US 10,380,060 B2Granted
Low-pincount high-bandwidth memory and memory bus
AssigneeEtron Technology, Inc.
InventorRichard Dewitt Crisp
Life of this patent
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AssigneeEtron Technology, Inc.
InventorRichard Dewitt Crisp
Estimating the term…
A memory subsystem is provided, including a memory controller integrated circuit (IC), a memory bus and a memory IC, all which use fewer signals than common DDR type memory of the same peak bandwidth. Using no more than 22 switching signals, the subsystem can transfer data over 3000 Megabytes/second across the bus interconnecting the ICs. Signal count reduction is attained by time-multiplexing address/control commands onto at least some of the same signals used for data transfer. A single bus signal is used to initiate bus operation, and once in operation the single signal can transfer addressing and control information to the memory IC concurrent with data transfer via a serial protocol based on 16 bit samples of this single bus signal. Bus bandwidth can be scaled by adding additional data and data strobe IO signals. These additional data bus signals might be used only for data and data mask transport. The physical layout of one version of the memory IC dispatches switching signal terminals adjacent to one short edge of the memory die to minimize the die area overhead for controller IC memory interface circuitry when used in a stacked die multi-chip package with said memory controller IC. The memory IC interface signal placement and signal count minimize signal length and circuitry for the memory bus signals.
A bus configured to interconnect at least one memory storage integrated circuit (IC) to a controller IC, the bus comprising:
A bus for interconnecting at least one memory IC with a controller IC wherein the bus is adapted to transfer memory commands and data using the same conductors wherein the bus is comprised of 16 conductors adapted to transport memory commands and data, two conductors adapted to transport clocks, and no more than five additional conductors adapted to transport data strobe and memory control signals and where the bus is adapted to transfer data at a peak bandwidth of at least 3000 Megabytes per second, wherein a single conductor is adapted to transport, from the controller IC to the memory IC concurrent with the transfer of data, a serial command that can direct the operation of the memory IC by providing address and data transfer control information to the memory IC.
A means for interconnecting at least one memory storage integrated circuit (IC) to a controller IC, comprising:
Dependencies are inferred from the claim text.