Memory bus MR register programming process
AssigneeIntel Corporation
InventorsTonia G. Morris, John V. Lovelace, John R. Goles
Life of this patent
Estimating the term…
Abstract
A method performed by a memory chip is described. The method includes receiving an activated chip select signal. The method also includes receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip. The method also includes receiving the next portion of the identifier on a portion of the memory chip's data inputs. The method also includes repeating the receiving of the activated chip select signal, the command code and the next portion until the entire identifier has been received and storing the entire identifier in a register.
Claims22
A memory chip, comprising:
- a) a first register to store an identifier of the memory chip;
- b) a second register to store an identifier of a targeted chip, said targeted chip identified by a command code issued on a command/address (CA) bus of a memory channel;
- c) data inputs to be coupled to the memory channel's data bus, the data inputs to receive the identifier of the memory chip;
- d) logic circuitry to cause said memory chip to:
- i) execute said command code's corresponding command if said identifier of said memory chip matches said identifier of said targeted chip;
- ii) ignore said command code's corresponding command if said identifier of said memory chip does not match said identifier of said targeted chip.
A memory controller, comprising:
- command/address (CA) bus circuitry to issue a command code on a CA bus of a memory channel to cause a rank of memory that is coupled to the memory channel to concurrently load respective identifiers into memory chips that the rank of memory is comprised of;
- and,
- data bus circuitry to place the respective identifiers on a data bus of the memory channel, the respective identifiers placed on data signal lines of the data bus that the memory chips are respectively coupled to.
A method performed by a memory chip, comprising:
- a) receiving an activated chip select signal;
- b) receiving, with the chip select signal being activated, a command code on a command/address (CA) bus that identifies a next portion of an identifier for the memory chip;
- c) receiving the next portion of the identifier on a portion of the memory chip's data inputs;
- d) repeating a), b) and c) for until the entire identifier has been received and storing the entire identifier in a register.
Dependencies are inferred from the claim text.