Disjointed virtual memory scheme with block bypass
AssigneeFriday Harbor LLC
InventorsJerome Vincent Coffin, Douglas A. Palmer
Life of this patent
Estimating the term…
Abstract
An improved virtual memory scheme designed for multi-processor environments that uses processor registers and a small amount of dedicated logic to eliminate the overhead that is associated with the use of page tables. The virtual addressing provides a contiguous virtual address space where the actual real memory is distributed across multiple memories. Locally, within an individual memory, the virtual space may be composed of discontinuous “real” segments or “chunks” within the memory, allowing bad blocks of memory to be bypassed without alteration of the virtual addresses. The delays and additional bus traffic associated with translating from virtual to real addresses are substantially reduced or eliminated.
Claims17
A method comprising:
- receiving, by a first device, data comprising a first address;
- extracting a first virtual address bits from the first address;
- translating the first virtual address bits into first physical address bits, comprising:
- accessing a register storing a first value equal to a bitwise exclusive OR of the first virtual address bits and the first physical address bits, the register having a register address based on the first virtual address bits;
- and
- performing a bitwise exclusive OR of the first value with the first virtual address bits to obtain the first physical address bits;
- routing the data to a first port of a plurality of ports based on the first physical address bits, wherein the first port is associated with a first physical memory of a plurality of separate physical memories;
- extracting second virtual address bits and address offset bits from the first address, as received via the first port;
- translating the second virtual address bits into second physical address bits;
- combining the second physical address bits and the address offset bits to determine a first physical address within the first physical memory;
- and
- reading from or writing to the first physical address.
A semiconductor chip, comprising:
- a first router;
- a plurality of separate physical memories each associated with a different port of a plurality of ports of the first router, including a first physical memory associated with a first port;
- a second router associated with the first port;
- and
- a digital comparator or gate logic circuit that receives one or more bits from a header of the data packet and outputs a selection signal indicating whether the first address is a virtual address or physical address based on the one or more bits,
- wherein the first router is configured to:
- receive a data packet comprising a first address,
- extract a first virtual address bits from the first address,
- translate the first virtual address bits into first physical address bits based on a first lookup table, and
- transmit the data packet via the first port based on the first physical address bits;
- and
- wherein the second router is configured to:
- receive the data packet via the first port,
- extract second virtual address bits and address offset bits from the first address,
- translate the second virtual address bits into second physical address bits based on a second lookup table, and
- combine the second physical address bits and the address offset bits to determine a first physical address within the first physical memory.
A device comprising:
- means for receiving data comprising an address;
- means for extracting first virtual address bits from the address by:
- accessing a register storing a first value equal to a bitwise exclusive OR of the first virtual address bits and the first physical address bits, the register having a register address based on the first virtual address bits;
- and
- performing a bitwise exclusive OR of the first value with the first virtual address bits to obtain the first physical address bits;
- means for translating the first virtual address bits into first physical address bits;
- means for routing the data to a first port of a plurality of ports;
- means for extracting second virtual address bits and address offset bits from the address;
- means for translating the second virtual address bits into second physical address bits;
- and
- means for determining a physical address in a physical memory using the second physical address bits and the address offset bits.
Dependencies are inferred from the claim text.