Achieving high bandwidth on ordered direct memory access write stream into a processor cache

A computer program product, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions readable by a processing circuit to cause the processing circuit to perform a method comprising:

• performing a key check, the key check being associated with a first ordered data store;
• signaling that a first memory node is ready to begin pipelining of a second ordered data store into the first memory node to an input/output (I/O) controller;
• returning a key response to a first cache indicating that the pipelining of the second ordered data store is ready to proceed;
• sending a ready signal indicating that the first memory node is ready to continue pipelining of the second ordered data store into the first memory node to the I/O controller, wherein the ready signal is triggered by receipt of the key response;
• performing a coherency check on the first ordered data store for a first ordered data store request received from the I/O controller;
• and
• detecting whether a delay condition exists in a distributed shared memory system with respect to the coherency check of the first ordered data store.

A computer system, comprising:

• one or more nodes comprising one or more processors in communication with one or more types of memory, the one or more types of memory being at least a plurality of caches;
• one or more input/output controllers;
• and
• one or more fabrics;
• wherein the computer system is configured to:
• perform a key check, the key check being associated with a first ordered data store;
• signal that a first memory node is ready to begin pipelining of a second ordered data store into the first memory node to an input/output (I/O) controller;
• return a key response to the first cache indicating that the pipelining of the second ordered data store is ready to proceed;
• send a ready signal indicating that the first memory node is ready to continue pipelining of the second ordered data store into the first memory node to the I/O controller, wherein the ready signal is triggered by receipt of the key response;
• perform a coherency check on the first ordered data store for a first ordered data store request received from the input/output (I/O) controller;
• and
• detect whether a delay condition exists in a distributed shared memory system with respect to the coherency check of the first ordered data store.