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US 10,379,971 B2Granted
Single and double chip space
AssigneeHewlett Packard Enterprise Development LP
InventorsGary Gostin, Erin A. Handgen
Life of this patent
Estimating the term…
Abstract
Techniques are provided for overcoming failures in a memory. One portion of the memory may operate in a single chip spare mode. Upon detection of an error in a single chip in the portion of the memory, a region of the portion of the memory may be converted to operate in a double chip spare mode. The memory may be accessed in both single and double chip spare modes.
Claims17
A device comprising:
- a memory controller to:
- access a first portion of a memory in a single chip spare mode;
- access a second portion of the memory in a double chip spare mode
- detect an error in a first region of the first portion of the memory;
- and
- convert the first region containing the error to a double chip spare mode.
3 more elements
A method comprising:
- detecting a single chip error in a first single chip spare mode region of memory;
- selecting a second single chip spare mode region of memory equal in size to the first region of memory;
- and
- converting the first and second region of memory from single chip spare mode to double chip spare mode.
1 more element
A method comprising:
- detecting an error in a single chip spare mode portion of a memory;
- determining a first region of the memory that is affected by the error;
- and
- converting the first region to a double chip spare mode.
1 more element
A device comprising:
- a memory controller to:
- access a first portion of a memory in a single chip spare mode;
- access a second portion of the memory in a double chip spare mode;
- detect an error in a first region of the first portion of the memory;
- select a second region in the first portion of the memory, the second region equal in size to the first region;
- and
- convert cache lines between the first and second regions to form a third region in double chip spare mode.
4 more elements
Dependencies are inferred from the claim text.