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US 10,379,947 B2Granted
Semiconductor device
AssigneeSK hynix Inc.
InventorsJae In Lee, Yong Mi Kim
Life of this patent
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Abstract
A semiconductor device includes a write read control circuit for outputting a write enable signal which is enabled in response to a write command, and a test mode signal; and an error correction circuit suitable for performing a calculation operation of determining an error information of input data in response to the write enable signal and then outputting an internal parity signal including the error information, and outputting internal data by delaying the input data in response to the write enable signal.
Claims20
A semiconductor device comprising:
- a write read control circuit suitable for outputting a write enable signal and a test mode signal in response to a write command;
- and
- an error correction circuit suitable for performing a calculation operation of determining error information of input data in response to the write enable signal, outputting an internal parity signal including the error information, and outputting internal data by delaying the input data in response to the write enable signal,
- wherein the test mode signal is a signal which includes time information of the calculation operation.
1 more element
A semiconductor device comprising:
- a write read control circuit suitable for outputting a write enable signal, a read enable signal, and a test mode signal in response to a write command and a read command;
- and
- an error correction circuit suitable for performing a first calculation operation of determining error information of input data in response to the write enable signal, outputting an internal parity signal including the error information, outputting internal data by delaying the input data in response to the write enable signal, and performing a second calculation operation of extracting an error correction information for correcting an error of the internal data from the internal parity signal in response to the read enable signal and then outputting output data by delaying the internal data,
- wherein the test mode signal is a signal which includes time information of the calculation operation.
1 more element
Dependencies are inferred from the claim text.