Bit error protection in cache memories
AssigneeAdvanced Micro Devices, Inc.
InventorsJohn Kalamatianos, Shrikanth Ganapathy, Steven Raasch
Life of this patent
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Abstract
A computing device having a cache memory (or “cache”) is described, as is a method for operating the cache. The method for operating the cache includes maintaining, in a history record, a representation of a number of bit errors detected in a portion of the cache. When the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, the method includes selecting, based on the history record, an error protection to be used for the portion of the cache memory. When the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, the method includes disabling the portion of the cache memory.
Claims20
A method for operating a cache memory in a computing device, the method comprising:
- storing, in a history record in an entry in a tag array of the cache memory that is associated with a portion of the cache memory, a representation of a number of bit errors detected in the portion of the cache memory during an access of the portion of the cache memory;
- when the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, selecting an error protection to be used for the portion of the cache memory during one or more subsequent accesses of the portion of the cache memory;
- and
- when the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, disabling the portion of the cache memory.
A computing device, comprising:
- one or more processing cores;
- and
- a cache that includes a tag array having a number of entries, each entry in the tag array including a history record, the cache configured to:
- store, in a history record in an entry in the tag array that is associated with a portion of the cache memory, a representation of a number of bit errors detected in the portion of the cache memory during an access of the portion of the cache memory;
- when the history record indicates that no bit errors or a single-bit bit error was detected in the portion of the cache memory, select an error protection to be used for the portion of the cache memory during one or more subsequent accesses of the portion of the cache memory;
- and
- when the history record indicates that a multi-bit bit error was detected in the portion of the cache memory, disable the portion of the cache memory.
Dependencies are inferred from the claim text.