Semiconductor device and memory access control method

A semiconductor device comprising:

• an address conversion circuit configured to receive, from a bus master, read/write requests including a first address for storing data in a memory and to generate a second address for storing an error detecting code generated from the data based on the first address;
• a write circuit configured to write the data at the first address when a write request for writing the data at the first address is received from the bus master, and to write the error detecting code at the second address received from the address conversion circuit;
• and
• a read circuit configured to read the data from the first address when a read request for reading the data stored at the first address is received from the bus master, and to read the error detecting code from the second address received from the address conversion circuit and detect an error based on the read data and the read error detecting code,
• wherein the address conversion circuit is configured to generate an address as the second address by modifying a value of at least one bit of the first address so as to offset a storing position of the error detecting code relative to a storing position of the data, and by inverting a value of, or permutating an order of, bits of a prescribed number of other bits of the first address,
• wherein, when a first mode is specified, the address conversion circuit is configured to generate an address as the second address by inverting the value of bits other than the at least one bit of the first address, and
• wherein, when a second mode is specified, the address conversion circuit configured to invert the value of bits other than the at least one bit of the first address, shift the bits except bits of a prescribed offset bit number from a lower order to a lower-order direction by the offset bit number, and modify the shifted bits of the offset bit number from a higher order to a preset offset value.