Pipeline delay detection during decoding by a data storage device
AssigneeSanDisk Technologies LLC
InventorsOmer Fainzilber, Ariel Navon, Alexander Bazarsky, David Gur, Stella Achtenberg
Life of this patent
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Abstract
A method of operation of a data storage device includes inputting data to a decoder of the data storage device. The method further includes sending a command to a memory of the data storage device in response to an indication of a pipeline delay associated with a decoding process to decode the data. The command indicates an operation to be performed at the memory to in response to the pipeline delay.
Claims20
A method of operation of a data storage device that includes a controller and a memory device, the method comprising:
- inputting data to a decoder of the controller;
- determining, with the controller, a characteristic associated with the data;
- generating, with the controller, an indication of a pipeline delay associated with a decoding process to decode the data in response to determining that the characteristic associated with the data satisfies a characteristic threshold;
- and
- controlling, with the controller, a memory interface of the controller to send a command to the memory device in response to the indication of the pipeline delay associated with the decoding process to decode the data, the command indicating an operation to be performed at the memory device in response to the pipeline delay.
An apparatus comprising:
- an error correcting code (ECC) engine configured to decode data using a decode operation;
- a circuit coupled to the ECC engine, the circuit configured to
- determine a characteristic associated with the data, and
- generate an indication of a pipeline delay associated with the decode operation in response to determining that the characteristic associated with the data satisfies a characteristic threshold;
- and
- a memory interface to a memory device, the memory interface configured to provide a command to the memory device to perform a read operation using a particular read technique in response to the indication of the pipeline delay.
An apparatus comprising:
- means for decoding data;
- means for predicting a pipeline delay associated with decoding of the data, wherein the means for predicting the pipeline delay determines a characteristic associated with the data and generates an indication of the pipeline delay associated with a decoding process to decode the data in response to determining that the characteristic associated with the data satisfies a characteristic threshold;
- and
- means for sending a command to a memory device, the command indicating a read operation to be performed at the memory device using a particular read technique to compensate for the pipeline delay in response to the indication of the pipeline delay,
- wherein the memory device is separate and distinct from the means for sending the command to the memory device.
Dependencies are inferred from the claim text.