Memory apparatus for in-chip error correction

A method of reducing access latency and improving data integrity by performing memory deduplication and a single chipkill mechanism in a computer memory, the method comprising:

• reading data, by a processor on a memory chip, from an array of memory chips;
• calculating, by the processor, one or more hashes based on the data;
• checking, by the processor, the one or more hashes against a physical line ID hash to determine whether the one or more hashes matches the physical line ID hash;
• detecting, by the processor, an error based on the one or more hashes being different from the physical line ID hash;
• correcting, by the processor, the error by sequentially flipping a data value of each bit, for up to all bits, of each memory chip of the array of the memory chips for up to all of the memory chips by performing a write operation using error-correcting code (ECC) to generate changed data until no error is detected;
• after flipping the data value of a respective bit of the bits, calculating, by the processor, at least one hash based on the changed data, and comparing the at least one hash based on the changed data against the physical line ID hash to determine whether the at least one hash matches the physical line ID hash;
• accepting, by the processor, the changed data as corrected data when the at least one hash matches the physical line ID hash;
• and
• outputting, by the processor, the corrected data.

A method of reducing access latency and improving data integrity by performing memory deduplication and a double chipkill mechanism in a computer memory, the method comprising:

• reading, by a processor on a memory chip, data from an array of memory chips;
• calculating, by the processor, one or more hashes based on the data;
• checking, by the processor, the one or more hashes against a physical line ID hash to determine whether the one or more hashes matches the physical line ID hash;
• detecting, by the processor, an error based on the one or more hashes being different from the physical line ID hash;
• correcting, by the processor, the error by sequentially flipping a data value of each bit, for up to all bits, of each pair of memory chips of the array of memory chips for up to all possible pairs of memory chips of the array of the memory chips by performing a write operation using error-correcting code (ECC) to generate changed data until no error is detected;
• after flipping the data value of a respective bit of the bits, calculating, by the processor, at least one hash based on the changed data, and comparing the at least one hash based on the changed data against the physical line ID hash to determine whether the at least one hash matches the physical line ID hash;
• accepting, by the processor, the changed data as corrected data when the at least one hash matches the physical line ID hash;
• and
• outputting, by the processor, the corrected data.