Performing a cyclic redundancy checksum operation responsive to a user-level instruction

A processor comprising:

• a cache;
• a plurality of 64-bit registers including a first 64-bit register to store source data and a second 64-bit register to store a 32-bit initial value in bits [31:0];
• and
• an execution unit coupled with the first and second 64-bit registers, the execution unit, responsive to a 32-bit cyclic redundancy check (CRC32) instruction of an instruction set architecture of the processor, to:
• perform CRC32 computations on the source data and the 32-bit initial value based on a polynomial value of 11EDC6F41H;
• and
• store a result of the CRC32 computations in a destination.

A system comprising:

• a processor, the processor comprising:
• a cache;
• a plurality of 64-bit registers including a first 64-bit register to store 64-bits of source data and a second 64-bit register to store a 32-bit initial value in bits [31:0];
• and
• an execution unit coupled with the first and second 64-bit registers, the execution unit, responsive to a 32-bit cyclic redundancy check (CRC32) instruction of an instruction set architecture of the processor, to:
• perform CRC32 computations on the 64-bits of source data and the 32-bit initial value based on a polynomial value of 11EDC6F41H;
• and
• store a result of the CRC32 computations in bits [31:0] of a 64-bit destination and zeroes in bits [63:32] of the 64-bit destination;
• and
• a peripheral component interconnect (PCI) Express bus coupled to the processor.

A system comprising:

• a processor, the processor comprising:
• a cache;
• a plurality of 64-bit registers including a first 64-bit register to store source data and a second 64-bit register to store a 32-bit initial value in bits [31:0];
• and
• an execution unit coupled with the first and second 64-bit registers, the execution unit, responsive to a 32-bit cyclic redundancy check (CRC32) instruction of an instruction set architecture of the processor, to:
• perform CRC32 computations on the source data and the 32-bit initial value based on a polynomial value of 11EDC6F41H;
• and
• store a result of the CRC32 computations in a destination;
• and
• a peripheral component interconnect (PCI) Express bus coupled to the processor.

A method performed by a processor, the method comprising:

• receiving 64-bits of source data from a first 64-bit register of a plurality of 64-bit registers;
• receiving a 32-bit initial value from bits [31:0] of a second 64-bit register of the plurality of 64-bit registers;
• executing a 32-bit cyclic redundancy check (CRC32) instruction, of an instruction set architecture of the processor, to perform operations comprising:
• performing CRC32 computations on the 64-bits of source data and the 32-bit initial value based on a polynomial value of 11EDC6F41H;
• and
• storing a result of the CRC32 computations in bits [31:0] of a 64-bit destination;
• and
• storing zeroes in bits [63:32] of the 64-bit destination.

An article comprising a machine-readable storage medium storing a 32-bit cyclic redundancy check (CRC32) instruction, of an instruction set architecture of a processor, that if executed by a machine is to cause the machine to perform operations comprising to:

• receive source data from a first 64-bit register of a plurality of 64-bit registers;
• receive a 32-bit initial value from bits [31:0] of a second 64-bit register of the plurality of 64-bit registers;
• perform CRC32 computations on the source data and the 32-bit initial value based on a polynomial value of 11EDC6F41H;
• and
• store a result of the CRC32 computations in a destination.