Memory architecture including response manager for error correction circuit
AssigneesSTMicroelectronics International N.V., STMicroelectronics S.r.l.
InventorsOm Ranjan, Riccardo Gemelli, Abhishek Gupta
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AssigneesSTMicroelectronics International N.V., STMicroelectronics S.r.l.
InventorsOm Ranjan, Riccardo Gemelli, Abhishek Gupta
Estimating the term…
A memory includes error correction circuitry that receives a data packet, outputs a correctable error flag indicating presence or absence of a correctable error in the data packet, and outputs an uncorrectable error flag indicating presence or absence of an uncorrectable error in the data packet. A response manager, operating in availability mode, generates output indicating that a correctable error was present if the correctable error flag indicates presence thereof, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof. In a coverage mode, the response manager generates an output indicating that a correctable error was potentially present but should be treated as an uncorrectable error if the correctable error flag indicates presence of the correctable error, and generates an output indicating that an uncorrectable error was present if the uncorrectable error flag indicates presence thereof.
A circuit, comprising:
A circuit, comprising:
A method of operating an electronic device, comprising:
Dependencies are inferred from the claim text.