Programmable clock monitor
AssigneeXilinx, Inc.
InventorsLester S. Sanders, Shravanthi Katam, Abhinaya Katta, Jayaram Pvss
Life of this patent
Estimating the term…
Abstract
An apparatus can include an interface circuit configured to receive an operating parameter and a control circuit coupled to the interface circuit and configured to store the operating parameter. The apparatus also can include a clock error detection circuit coupled to the control circuit. The clock error detection circuit can be configured to detect a clock error condition on a clock signal based upon the operating parameter and, responsive to detecting the clock error condition, generate a signal indicating an occurrence of the clock error condition.
Claims18
An apparatus for monitoring clock signals, comprising:
- an interface circuit configured to receive an operating parameter;
- a control circuit coupled to the interface circuit and configured to store the operating parameter;
- and
- a clock error detection circuit coupled to the control circuit, wherein the clock error detection circuit is programmable during operation using the operating parameter to detect a clock error condition on a clock signal and, responsive to detecting the clock error condition, generate a signal indicating an occurrence of the clock error condition;
- wherein the clock error condition is defined, at least in part, by the operating parameter and the clock error detection circuit is configured to detect a clock glitch error condition by comparing a number of reference clock cycles that occur while a frequency divided version of the clock signal is high with a number of reference clock cycles that occur while the frequency divided version of the clock signal is low and determining that the numbers of the reference clock cycles are not within a predetermined range of one another.
A method of monitoring clock signals, comprising:
- receiving, in a clock monitor circuit, an operating parameter;
- programming a clock error detection circuit of the clock monitor circuit with the operating parameter during operation;
- detecting a clock error condition on a clock signal using the clock error detection circuit, wherein the clock error condition is defined, at least in part, by the operating parameter, wherein the clock error detection circuit is configured to detect a clock glitch error condition by comparing a number of reference clock cycles that occur while a frequency divided version of the clock signal is high with a number of reference clock cycles that occur while the frequency divided version of the clock signal is low and determining that the numbers of the reference clock cycles are not within a predetermined range of one another;
- and
- responsive to detecting the clock error condition, generating a signal indicating an occurrence of the clock error condition.
Dependencies are inferred from the claim text.