Controlling a performance state of a processor using a combination of package and thread hint information

A non-transitory machine-readable medium having stored thereon instructions, which if performed by a machine cause the machine to perform a method comprising:

• storing, in a first plurality of fields of a first configuration storage of a processor, processor performance state hints, the processor performance state hints associated with an operating system and to convey hint information for use in determination of a performance state for at least a portion of the processor;
• storing, in a first plurality of fields of a second configuration storage of the processor, thread performance state hints, the thread performance state hints associated with a first thread and to convey hint information for use in determination of a performance state for a first processing engine of the processor on which the first thread is to execute;
• storing, in the processor, a plurality of valid indicators associated with the thread performance state hints;
• determining autonomously, via a power controller of the processor, the performance state for the first processing engine on which the first thread executes based on a combination of the processor performance state hints and the thread performance state hints;
• and
• controlling, via the power controller, the first processing engine to operate at the performance state.

A system comprising:

• a processor having a plurality of cores, at least one of the plurality of cores to execute in a multi-threaded mode, the processor further including:
• a first storage having a first set of fields to store a set of common performance state request settings to convey hints for use in determination of a performance state for at least a portion of the processor;
• a second storage having the first set of fields to store a set of thread performance state request settings to convey hints for use in determination of a performance state for a first core of the processor on which a thread is to execute;
• and
• a controller to autonomously determine and control the performance state of the first core based on a combination of at least one of the set of common performance state request settings and at least one of the set of thread performance state request settings;
• and
• at least one voltage regulator coupled to the processor.