US 10,379,887 B2 · Performance-imbalance-monitoring processor features

Abstract

The current application is directed to architected hardware support within computer processors for detecting and monitoring various types of potential performance imbalances with respect to simultaneously executing hardware threads in simultaneous multi-threading (“SMT”) processors and SMT-processor cores. The architected hardware support may include various types of performance-imbalance-monitoring registers that accumulate indications of performance imbalances and that can be used, by performance-monitoring software and by human analysts to detect performance-degrading conflicts between simultaneously executing hardware threads. Such conflicts can be ameliorated by changing the scheduling of virtual machines, tasks, and other computational entities, by redesigning and re-implementing all or portions of performance-limited and performance-degrading applications, by altering resource-allocation strategies, and by other means. In addition, performance imbalance detection and monitoring can be used to provide accurate, computational-throughput-based accounting in cloud-computing environments.

Claims19

Dependent claims

A performance-imbalance-monitoring register associated with a component or resource within a processor, the component or resource shared, or variably partitioned, among two or more hardware threads executing within the processor, the performance-imbalance-monitoring register comprising:

a processor register that stores accumulated indications of potential performance imbalances that arise from contention for the component or resource by two or more of the hardware threads when one of the hardware threads contending for the component or resource is using less than a threshold portion of the component or resource and when a resource-exhaustion event associated with the component or resource, which may be recorded in a performance-monitoring register within the processor, has occurred to the detriment of the hardware thread using less than a threshold portion of the component or resource;
and
processor logic that detects a potential performance imbalance when handling the resource-exhaustion event and accordingly updates the processor register.

A virtualization layer within a computer system that assigns each of two or more virtual machines to execute according to an execution schedule within a different one of two or more hardware threads within each of multiple processors, the virtualization layer comprising:

a virtual-machine-monitor that virtualizes physical processors to create virtual processors on which each of the virtual machines executes, each physical processor including performance-monitoring and performance-imbalance-monitoring registers associated with components within the processor that are flexibly partitioned among, or shared by, the hardware threads, each performance-imbalance-monitoring register associated with a component or resource within a processor and storing accumulated indications of potential performance imbalances that arise from contention for the component or resource by two or more of the hardware threads when one of the hardware threads contending for the component or resource is using less than a threshold portion of the component or resource and when a resource-exhaustion event associated with the component or resource has occurred to the detriment of the hardware thread using less than a threshold portion of the component or resource;
a kernel that manages memory, communications, and data-storage machine resources on behalf of executing virtual machines;
and
a scheduling component that that intermittently uses values in the performance-monitoring and performance-imbalance-monitoring registers to reassign virtual machines to hardware threads and reschedule execution of virtual machines in order to optimize computational throughput and performance of the virtual machines.

1 more element

Dependencies are inferred from the claim text.

Performance-imbalance-monitoring processor features

Life of this patent

Performance-imbalance-monitoring processor features

Life of this patent

Abstract

Claims19