Supporting soft reboot in multi-processor systems without hardware or firmware control of processor state

A non-transitory computer readable medium comprising instructions to be executed in a secondary processor pursuant to a soft reboot of system software, wherein the instructions, when executed in the secondary processor, cause the secondary processor to perform a method comprising:

• storing code to be executed by the secondary processor in a region of physical memory;
• building first page tables to map the code into a first address space and second page tables to identically map the code into a second address space;
• fetching a first instruction of the code from a first location in the physical memory based on a first virtual address and active page tables, wherein the first virtual address is a virtual address in the first address space;
• executing the code beginning with the first instruction to switch the active page tables from the first page tables to the second page tables;
• and
• after the active page tables have been switched from the first page tables to the second page tables, (i) fetching a next instruction of the code to be executed from a second location in the physical memory using a second virtual address, which is identically mapped to a corresponding machine address, (ii) turning off a memory management unit of the secondary processor, and (iii) executing a waiting loop until a predetermined location in the physical memory changes in value, and (iv) exiting the waiting loop and executing an initialization code at a physical memory address corresponding to the changed value.

A computer system comprising:

• a primary processor running system software;
• and
• one or more secondary processors,
• wherein, when the primary processor initiates a soft reboot of the system software, each of the secondary processors performs the steps of:
• storing code to be executed by the secondary processor in a region of physical memory;
• building first page tables to map the code into a first address space and second page tables to identically map the code into a second address space;
• fetching a first instruction of the code from a first location in the physical memory based on a first virtual address and active page tables, wherein the first virtual address is a virtual address in the first address space;
• executing the code beginning with the first instruction to switch the active page tables from the first page tables to the second page tables;
• and
• after the active page tables have been switched from the first page tables to the second page tables, (i) fetching a next instruction of the code to be executed from a second location in the physical memory using a second virtual address, which is identically mapped to a corresponding machine address, (ii) turning off a memory management unit of the secondary processor, and (iii) executing a waiting loop until a predetermined location in the physical memory changes in value, and (iv) exiting the waiting loop and executing an initialization code at a physical memory address corresponding to the changed value.