Electronic apparatus, VLIW processor and control methods for updating a multi-cycle no operation (NOP) instruction

A very long instruction word (VLIW) processor, comprising:

• a memory;
• and
• a plurality of function units,
• wherein the VLIW processor is configured to:
• control the memory to store compiled data,
• control the plurality of function units to process the compiled data,
• sequentially execute at least one VLIW instruction based on the compiled data and
• shorten, if the at least one VLIW instruction being executed is a predetermined instruction, if an operand of the at least one VLIW instruction comprises a predetermined value, and if a multi-cycle no operation (nop) instruction synchronized with the at least one VLIW instruction is identified within a cycle corresponding to a latency of the at least one VLIW instruction, a cycle of the multi-cycle nop instruction based on information included in the multi-cycle nop instruction.

A control method of a very long instruction word (VLIW) processor, the control method comprising:

• sequentially executing at least one VLIW instruction based on compiled data;
• changing a latency of the at least one VLIW instruction, if the at least one VLIW instruction being executed is a predetermined VLIW instruction and an operand of the at least one VLIW instruction comprises a predetermined value;
• processing the at least one VLIW instruction during the changed latency;
• and
• shortening, if a multi-cycle no operation (nop) instruction for the plurality of function units is identified within the cycle corresponding to the latency of the at least one VLIW instruction and an end cycle of another VLIW instruction which is being currently executed is within the cycle corresponding to the latency of the at least one VLIW instruction, a cycle of the multi-cycle nop instruction based on a cycle difference between the end cycle of the at least one VLIW instruction and the another VLIW cycle.