Selection of instructions to be issued

A method for selecting instructions to issue, the method comprising:

• receiving, by an instruction scheduling circuit, a plurality of entries, each entry including an instruction, a validity indication, and at least one respective attribute;
• partitioning, by the instruction scheduling circuit, the plurality of entries into a plurality of entry sets of respective entries;
• determining, by the instruction scheduling circuit, a plurality of ordered entry sets by ordering the respective entries of each entry set according to the respective attributes of the respective entries of the ordered entry set, wherein ordering the respective entries of an entry set includes:
• producing, via a plurality of comparators and for at least a first pair of entries of the entry set, a plurality of respective comparison results by comparing the respective attribute of a first entry of the first pair of entries with the respective attribute of a second entry of the first pair of entries;
• determining respective position indicators of the entries of the entry set according to the plurality of respective comparison results produced for at least the first pair of entries of the entry set;
• and
• producing a re-ordered entry set, the re-ordered entry set including the entries of the entry set that are re-ordered according to the respective position indicators;
• generating, by the instruction scheduling circuit, a set ordering for the plurality of entry sets according to a function of the respective attributes of the respective entries of each entry set;
• and
• selecting, by the instruction scheduling circuit and based on at least the set ordering, a plurality of instructions from the plurality of ordered entry sets for issuance to a processor core.

A system-on-chip comprising:

• a processor core to execute processor-executable instructions;
• an instruction buffer including a plurality of entries, each entry including an instruction, a validity indication, and at least one respective attribute;
• and
• an instruction scheduling circuit to:
• partition the plurality of entries of the instruction buffer into a plurality of entry sets of respective entries, the plurality of entry sets including at least a first entry set and a second entry set;
• determine a plurality of ordered entry sets by ordering the respective entries of each entry set of the plurality of entry sets according to the respective attributes of the entries of that entry set of the plurality of entry sets;
• determine a set ordering for the plurality of ordered entry sets according to a function of the respective attributes of the respective entries of each ordered entry set;
• and
• select, based on the set ordering for the plurality of ordered entry sets, a plurality of instructions from the plurality of ordered entry sets for issuance to the processor core,
• wherein the instruction scheduling circuit comprises an entry ordering circuit to order entries of at least the first entry set of the plurality of entry sets, the entry ordering circuit including:
• a plurality of comparators to generate respective outputs by comparing, for at least a first pair of entries of the first entry set, the respective attribute of a first entry of the first pair of entries with the respective attribute of a second entry of the first pair of entries;
• a position determining circuit to determine respective position indicators of the entries of the first entry set according to the respective outputs of the plurality of comparators;
• and
• an output select circuit to output a re-ordered entry set, the re-ordered entry set including the entries of the first entry set that are re-ordered according to the respective position indicators.