Dynamic sequential instruction prefetching

A data processing system, comprising:

• a data storage subsystem;
• and
• a processor coupled to the data storage subsystem, wherein the processor is configured to:
• in response to a cache line address missing in an instruction cache, allocate an entry in a prefetch filter queue for the cache line address;
• in response to the cache line address hitting in the instruction cache subsequent to the cache line address missing in the instruction cache, update an associated prefetch value for the entry in the prefetch filter queue, wherein the associated prefetch value corresponds to a number of entries in the prefetch filter queue that have cache line addresses that are sequential to the cache line address;
• in response to the entry being aged-out of the prefetch filter queue, allocate an entry in a backing array for the cache line address and the associated prefetch value;
• in response to determining that prefetching is required for the cache line address subsequent to the entry being aged-out of the prefetch filter queue, access the backing array to determine the associated prefetch value for the cache line address;
• and
• in response to the backing array including the entry for the cache line address and the prefetch filter queue not including the entry for the cache line address, prefetch a cache line at the cache line address and a number of sequential cache lines that follow the cache line address, as specified by the associated prefetch value in the backing array, into the instruction cache.

A method of operating a processor, comprising:

• in response to a cache line address missing in an instruction cache, allocating, by an instruction fetch unit (IFU), an entry in a prefetch filter queue for the cache line address;
• in response to the cache line address hitting in the instruction cache subsequent to the cache line address missing in the instruction cache, updating, by the IFU, an associated prefetch value for the entry in the prefetch filter queue, wherein the associated prefetch value corresponds to a number of entries in the prefetch filter queue that have cache line addresses that are sequential to the cache line address;
• in response to the entry being aged-out of the prefetch filter queue, allocating, by the IFU, an entry in a backing array for the cache line address and the associated prefetch value;
• in response to determining that prefetching is required for the cache line address subsequent to the entry being aged-out of the prefetch filter queue, accessing, by the IFU, the backing array to determine the associated prefetch value for the cache line address;
• and
• in response to the backing array including the entry for the cache line address and the prefetch filter queue not including the entry for the cache line address, prefetching, by the IFU, a cache line at the cache line address and a number of sequential cache lines that follow the cache line address, as specified by the associated prefetch value in the backing array, into the instruction cache.