Processors, methods, systems, and instructions to load multiple data elements to destination storage locations other than packed data registers

A method performed by a processor comprising:

• receiving an instruction at the processor, the instruction indicating a packed data register that stores a source packed memory address information, the source packed memory address information including a plurality of memory address information data elements, and the instruction indicating a single destination memory address;
• loading a plurality of data elements from a plurality of memory addresses that each correspond to a different one of the plurality of memory address information data elements in response to the instruction;
• and
• storing the plurality of loaded data elements contiguously in a destination storage location, which corresponds to the single destination memory address, in response to the instruction.

A system to process instructions comprising:

• an interconnect;
• a processor coupled with the interconnect, the processor to receive an instruction, the instruction to indicate a packed data register that is to store a source packed memory address information, the source packed memory address information to include a plurality of memory address information data elements, and the instruction to indicate a scalar register that is to store a single destination memory address information, the processor, in response to the instruction, to load a plurality of data elements from a plurality of memory addresses that are each to correspond to a different one of the plurality of memory address information data elements, and store the plurality of loaded data elements contiguously in a destination storage location, wherein the destination storage location does not include a packed data register, and wherein the destination storage location corresponds to the single destination memory address information;
• and
• a memory coupled with the interconnect.

An article of manufacture comprising a non-transitory machine-readable storage medium, the non-transitory machine-readable storage medium storing a plurality of instructions including an instruction, the instruction, if performed by a machine, is to cause the machine to perform operations comprising:

• access a source packed memory address information from a packed data register that is to be indicated by the instruction, the source packed memory address information to include a plurality of memory address information data elements;
• generate a single destination memory address from a single destination memory address information to be accessed from a general-purpose register to be indicated by the instruction;
• load a plurality of data elements from a plurality of memory addresses that are each to correspond to a different one of the plurality of memory address information data elements;
• and
• store the plurality of loaded data elements contiguously in a destination storage location that corresponds to the single destination memory address.

A processor comprising:

• at least one cache;
• a plurality of packed data registers;
• a decode unit to decode an instruction, the instruction to indicate a source memory address information, and the instruction to indicate a destination memory address information;
• and
• an execution unit coupled with the decode unit, the execution unit, in response to the instruction, to:
• non-temporally load a data element from a source memory address that corresponds to the memory address information, in which the loaded data element is not to be cached in any cache lines of the at least one cache that correspond to the source memory address for the data element;
• and
• cache the loaded data element in a cache line in the at least one cache, wherein the cache line corresponds to the destination memory address information.