Processor instructions for determining two minimum and two maximum values

A processor comprising:

• hardware circuitry configured to implement an instruction set architecture (ISA) including a 128-bit SIMD (Single Instruction Multiple Data) instruction configured, when executed, to output:
• a first pair of minimum values among a first set of input values including a first pair of current minimum values and a first comparison value;
• and
• a second pair of minimum values among a second set of input values including a second pair of current minimum values and a second comparison value.

A method for determining the smallest two values in a data set having a plurality of data elements implemented on a processor comprising hardware circuitry configured to implement an instruction set architecture (ISA) including a 128-bit SIMD (Single Instruction Multiple Data) instruction configured, when executed, to output a first pair of minimum values among a first set of input values including a first pair of current minimum values and a first comparison value, and a second pair of minimum values among a second set of input values including a second pair of current minimum values and a second comparison value, the method

• comprising:
• partitioning the data set into first and second halves of the data set;
• determining a first pair of minimum values corresponding to the first half of the data set;
• determining a second pair of minimum values corresponding to the second half of the data set;
• and
• determining the two smallest values among the first pair of minimum values and the second pair of minimum values,
• wherein the first pair and second pair of minimum values are determined in parallel by one of iteratively or recursively executing the 128-bit SIMD instruction on the processor in conjunction with iterating through the first and second halves of the data set.