Data accumulation apparatus and method, and digital signal processing device

A data accumulation means by using a data accumulation device, wherein the data accumulation device comprises:

• an accumulation tree module for accumulating input data to partial sum data in the form of a tree structure;
• a register module including a plurality of groups of registers for storing the partial sum data;
• and
• a control module, the control module comprising:
• a gating signal generation circuit for generating a data gating signal to control the accumulation tree module to filter the input data not required to be accumulated;
• a data register signal generation circuit for generating a data register selection signal to control a storage position of the partial sum data in the register module;
• a data read signal generation circuit for generating a data read selection signal to select one or more of the partial sum data registered in one register of the register module;
• and
• a flag signal generation circuit for generating a flag signal to perform accumulation and selection control, so as to output a result obtained after adding the partial sum data selected by the data read selection signal to the partial sum data output from the accumulation tree module in a current clock cycle as updated partial sum data, or directly output the partial sum data output from the accumulation tree module in the current clock cycle, wherein the output data are selected to be registered in the register, or output to an external memory based on control of the flag signal and the data register selection signal;
• the data accumulation means, comprising:
• step 1, in which a gating signal generation circuit of a control circuit generates and transmits a data gating signal to an accumulation tree module;
• step 2, in which the accumulation tree module judges which input data are required to be accumulated, and accumulates the input data required to be accumulated to partial sum data in the form of a tree structure based on the data gating signal;
• step 3, in which a data register signal generation circuit of the control circuit generates and transmits a data register selection signal to a register module, and based on the data register selection signal, the register module registers the partial sum data in a register selected by the data register selection signal;
• step 4, in which a data read signal generation circuit of the control circuit generates and transmits a data read selection signal to the register module to select one or more of the partial sum data registered in one register of the register module;
• step 5, in which a flag signal generation circuit of the control circuit generates a flag signal to perform accumulation and selection control, so as to output a result obtained after adding the partial sum data selected by the data read selection signal to the partial sum data output from the accumulation tree module in a current clock cycle as updated partial sum data, or directly output the partial sum data output from the accumulation tree module in the current clock cycle, wherein the output data are selected to be registered in the register, or output to an external memory based on control of the flag signal and the data register selection signal;
• and
• step 6, in which the output data are selected to be registered in the register, or output to an external memory based on control of the flag signal and the data register selection signal.

A digital signal processing device comprising the data accumulation device, wherein the data accumulation device comprises:

• an accumulation tree module for accumulating input data to partial sum data in the form of a tree structure;
• a register module including a plurality of groups of registers for storing the partial sum data;
• and
• a control module, the control module comprising:
• a gating signal generation circuit for generating a data gating signal to control the accumulation tree module to filter the input data not required to be accumulated;
• a data register signal generation circuit for generating a data register selection signal to control a storage position of the partial sum data in the register module;
• a data read signal generation circuit for generating a data read selection signal to select one or more of the partial sum data registered in one register of the register module;
• and
• a flag signal generation circuit for generating a flag signal to perform accumulation and selection control, so as to output a result obtained after adding the partial sum data selected by the data read selection signal to the partial sum data output from the accumulation tree module in a current clock cycle as updated partial sum data, or directly output the partial sum data output from the accumulation tree module in the current clock cycle, wherein the output data are selected to be registered in the register, or output to an external memory based on control of the flag signal and the data register selection signal.

A digital signal processing means by using a data accumulation device, wherein the data accumulation device comprises:

• an accumulation tree module for accumulating input data to partial sum data in the form of a tree structure;
• a register module including a plurality of groups of registers for storing the partial sum data;
• and
• a control module, the control module comprising:
• a gating signal generation circuit for generating a data gating signal to control the accumulation tree module to filter the input data not required to be accumulated;
• a data register signal generation circuit for generating a data register selection signal to control a storage position of the partial sum data in the register module;
• a data read signal generation circuit for generating a data read selection signal to select one or more of the partial sum data registered in one register of the register module;
• and
• a flag signal generation circuit for generating a flag signal to perform accumulation and selection control, so as to output a result obtained after adding the partial sum data selected by the data read selection signal to the partial sum data output from the accumulation tree module in a current clock cycle as updated partial sum data, or directly output the partial sum data output from the accumulation tree module in the current clock cycle, wherein the output data are selected to be registered in the register, or output to an external memory based on control of the flag signal and the data register selection signal;
• the digital signal processing means, comprising:
• step 1, in which a gating signal generation circuit of a control circuit generates and transmits a data gating signal to an accumulation tree module;
• step 2, in which the accumulation tree module judges which input data are required to be accumulated, and accumulates the input data required to be accumulated to partial sum data in the form of a tree structure based on the data gating signal;
• step 3, in which a data register signal generation circuit of the control circuit generates and transmits a data register selection signal to a register module, and based on the data register selection signal, the register module registers the partial sum data in a register selected by the data register selection signal;
• step 4, in which a data read signal generation circuit of the control circuit generates and transmits a data read selection signal to the register module to select one or more of the partial sum data registered in one register of the register module;
• step 5, in which a flag signal generation circuit of the control circuit generates a flag signal to perform accumulation and selection control, so as to output a result obtained after adding the partial sum data selected by the data read selection signal to the partial sum data output from the accumulation tree module in a current clock cycle as updated partial sum data, or directly output the partial sum data output from the accumulation tree module in the current clock cycle, wherein the output data are selected to be registered in the register, or output to an external memory based on control of the flag signal and the data register selection signal;
• and
• step 6, in which the output data are selected to be registered in the register, or output to an external memory based on control of the flag signal and the data register selection signal.