Variable precision floating-point multiplier

Multiplier circuitry on an integrated circuit die, comprising:

• a partial product generator configured to receive a first input signal and a second input signal;
• a compressor tree circuit configured to receive signals from the partial product generator and to generate a first set of sum and carry vectors and a second set of sum and carry vectors;
• and
• carry propagate adder circuitry configured to receive the first set of sum and carry vectors and the second set of sum and carry vectors from the compressor tree circuit, wherein the carry propagate adder circuitry is operable to generate a first floating-point multiplier output having a first mantissa width in a first mode and to generate a second floating-point multiplier output having a second mantissa width that is different than the first mantissa width in a second mode, wherein the multiplier circuitry is configured to support a given number of exponent bits in the first mode and to support the given number of exponent bits in the second mode, wherein the difference between the first mantissa width and the second mantissa width is less than or equal to four, and wherein the lower bits in the first and second input signals are used to round the least significant bit of the first floating-point multiplier output in the first mode and to round the least significant bit of the second floating-point multiplier output in the second mode.

Multiplier circuitry on an integrated circuit die, comprising:

• a partial product generator configured to receive a first input signal and a second input signal;
• a compressor tree circuit configured to receive signals from the partial product generator and to generate a first set of sum and carry vectors and a second set of sum and carry vectors;
• and
• carry propagate adder circuitry configured to receive the first set of sum and carry vectors and the second set of sum and carry vectors from the compressor tree circuit, wherein the carry propagate adder circuitry is operable to generate a floating-point multiplier output using a first mode that is smaller than a single-precision floating-point format, wherein the carry propagate adder circuitry comprises a carry propagate adder configured to handle a maximum of 12 mantissa bits, and wherein the first mode uses 8 exponent bits and 7-11 mantissa bits.