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US 10,379,786 B2Granted
Semiconductor devices
AssigneeSK hynix Inc.
InventorsMun Seon Jang, Saeng Hwan Kim, Chang Ki Baek, Jae Woong Yun
Life of this patent
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Abstract
A semiconductor device may include a data storage region, a parity storage region and an error correction circuit. The data storage region may be configured to store first data and second data. The parity storage region may be configured to store a parity. The error correction circuit may be configured to correct an error of the first data or an error of the second data and the parity, based on a transmission selection signal.
Claims19
A semiconductor device comprising:
- a data storage region configured to store first data and second data;
- a parity storage region configured to store a parity;
- and
- an error correction circuit configured to correct an error of the first data and an error of the second data and the parity, combined together, when a transmission selection signal is disabled, and configured to correct the error of the first data, separate from the error of the second data and the parity, when the transmission selection signal is enabled, wherein the error correction circuit includes a first syndrome signal generation circuit configured to generate a first syndrome signal from the first data, a second syndrome signal generation circuit configured to generate a second syndrome signal from the second data and the parity, a transmission control circuit configured to output the first syndrome signal as a first transmission syndrome signal or a second transmission syndrome signal based on the transmission selection signal, a signal synthesis circuit configured to generate a synthesized syndrome signal from the first transmission syndrome signal and the second syndrome signal, and a decode signal generation circuit configured to decode the second transmission syndrome signal and the synthesized syndrome signal to generate a first decode signal and a second decode signal based on the transmission selection signal.
1 more element
A semiconductor device comprising:
- an error correction circuit configured to correct an error of a first data and an error of a second data and a parity, combined together, to generate a first corrected data and a second corrected data or configured to separately correct the error of the first data and the error of the second data and the parity to generate the first corrected data and the second corrected data, in response to a transmission selection signal;
- a fail signal generation circuit configured to generate a first fail signal and a second fail signal from the first corrected data and the second corrected data;
- a pre-fail signal generation circuit configured to generate a first pre-fail signal and a second pre-fail signal from the first and second data and the parity in response to the transmission selection signal and the first and second fail signals;
- and
- a repair signal generation circuit configured to generate a first repair signal and a second repair signal in response to the first and second pre-fail signals, the first and second fail signals, and a control signal, wherein the first repair signal is enabled to repair a storage region stored the first data.
2 more elements
Dependencies are inferred from the claim text.