Operation interlocking in an address-sliced cache system

A system for interlocking operations in an address-sliced cache system comprising:

• a plurality of computer processor chips;
• and
• a system controller coupled to the plurality of computer processor chips, wherein the system controller is configured to:
• determine whether a dynamic memory relocation operation is in process;
• based on determining that the dynamic memory relocation operation is in process, serialize a key operation to maintain a sequenced order of completion of the key operation across a plurality of slices and pipes in the address-sliced cache system;
• and
• based on determining that the dynamic memory relocation operation is not in process, allow a plurality of key operation requests to launch in parallel across two or more of the plurality of slices and pipes in parallel in the address-sliced cache system while ensuring that only one instance of the key operations is in process across all of the plurality of slices and pipes at a same time by launching the plurality of key operation requests from the plurality of slices and pipes of a first cache control to a second cache control, using a dedicated resource per port at the second cache control to queue the plurality of key operation requests in parallel from the plurality of slices and pipes in parallel, identifying one pipe of the plurality of slices and pipes in the second cache control as a master pipe, and processing the plurality of key operation requests by pipes of the plurality of slices and pipes in a same order as the master pipe based on an indication broadcast on an encoded tag bus from the master pipe of a current instance of the plurality of key operation requests being processed.

A computer program product for interlocking operations in an address-sliced cache system, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by processing circuitry to cause the processing circuitry to perform:

• determining whether a dynamic memory relocation operation is in process in the address-sliced cache system;
• based on determining that the dynamic memory relocation operation is in process, serializing a key operation to maintain a sequenced order of completion of the key operation across a plurality of slices and pipes in the address-sliced cache system;
• and
• based on determining that the dynamic memory relocation operation is not in process, allowing a plurality of key operation requests to launch in parallel across two or more of the plurality of slices and pipes in parallel in the address-sliced cache system while ensuring that only one instance of the key operations is in process across all of the plurality of slices and pipes at a same time by launching the plurality of key operation requests from the plurality of slices and pipes of a first cache control to a second cache control, using a dedicated resource per port at the second cache control to queue the plurality of key operation requests in parallel from the plurality of slices and pipes in parallel, identifying one pipe of the plurality of slices and pipes in the second cache control as a master pipe, and processing the plurality of key operation requests by pipes of the plurality of slices and pipes in a same order as the master pipe based on an indication broadcast on an encoded tag bus from the master pipe of a current instance of the plurality of key operation requests being processed.