Predictive scheduler for memory rank switching

A system for scheduling memory accesses, the system comprising:

• a plurality of ranks of memory, of which at most a total of r ranks are powered up concurrently, wherein r is less than the plurality of ranks;
• a processor coupled to the plurality of ranks of memory via one or more memory buses;
• one or more computer-readable storage media;
• and
• program instructions stored on one or more of the computer-readable storage media, which when executed cause the processor to perform a method comprising:
• in response to determining that fewer than r ranks are powered up:
• powering up a subset of requested powered down ranks of the plurality of ranks, such that the at most the total of r ranks is powered up, wherein the subset of requested powered down ranks of the plurality of ranks to be powered up comprises most frequently accessed requested powered down ranks of the plurality of ranks and is based on a number of memory requests received by each of the requested powered down ranks of the plurality of ranks within a defined time window corresponding to an expected length of a sequence of memory operations;
• and then
• in response to determining that fewer than the r ranks are powered up:
• powering up a subset of unrequested powered down ranks of the plurality of ranks, such that the at most the total of r ranks is powered up concurrently, wherein the subset of unrequested powered down ranks of the plurality of ranks to be powered up comprises the most frequently accessed unrequested powered down ranks of the plurality of ranks and is based on a number of memory requests received within the defined time window.