Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation

An apparatus, comprising:

• a memory array comprising a plurality of memory planes, wherein each of the plurality of memory planes comprises a plurality of memory cells;
• a plurality of read level voltage regulator circuits, wherein each read level voltage regulator circuit of the plurality of read level voltage regulator circuits is configured to provide a respective read level voltage signal for a corresponding memory plane of the plurality of memory planes;
• a controller configured to perform concurrent memory access operations on two or more of the plurality of memory planes, wherein, during the concurrent memory access operations, the controller is configured to control two or more of the plurality of read level voltage regulator circuits to provide the respective read level voltage signal;
• and
• a plurality of global access line decoder circuits, wherein a global access line decoder circuit of the plurality of global access line decoder circuits is coupled to a respective memory plane of the plurality of memory planes via a respective global access line bus, wherein, during a memory access operation, the global access line decoder circuit of the plurality of global access line decoder circuits is configured to provide the respective read level voltage signal to one of a plurality of global access lines of the respective global access line bus, wherein the global access line decoder circuit of the plurality of global access line decoder circuits is further configured to provide a respective pass voltage signal on each remaining global access line of the plurality of global access lines of the respective global access line bus.