Clock divide-by-three circuit

Abstract

A clock divider circuit receives an input clock signal having a first frequency (f) and generates an output signal having a frequency equal to f/N, where N is an odd integer. The clock divider circuit includes an edge counter to count a number of consecutive edges of the input clock signal having a first plurality, and to assert a control signal when a threshold number (N) of consecutive edges has been counted. The clock divider circuit also includes a frequency multiplier to generate an intermediate clock signal having a frequency equal to 2f/N by doubling the frequency of the control signal based at least in part on transitions of the input clock signal, and a frequency divider to generate an output clock signal having a frequency equal to f/N by halving the frequency of the intermediate clock signal.

Dependencies are inferred from the claim text.