Method and apparatus for simulation of lithography overlay
AssigneeQoniac GmbH
InventorBoris Habets
Life of this patent
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Abstract
A method for simulation of lithography overlay is disclosed which comprises storing alignment parameters used to align a semiconductor wafer prior to a lithography step; storing process control parameters used during the lithography step on the semiconductor wafer; storing overlay parameters measured after the lithography step; calculating alternative alignment parameters and alternative process control parameters. The alternative alignment parameters and the alternative process control parameters are added to cleansed overlay parameters to obtain simulated lithography overlay data.
Claims9
A manufacturing control method for controlling an exposure tool for projecting a pattern onto a surface of a semiconductor wafer by testing lithography overlay comprising:
- storing, in a non-volatile memory connected to a simulation processor, alignment corrections resulting from aligning, with an exposure tool, the surface of a semiconductor wafer with a light source and a projection optic, prior to a lithography step;
- storing in said non-volatile memory process control parameters, provided from an exposure controller and used, in addition to alignment corrections, by the exposure tool during the lithography step for projecting a pattern onto a surface of the semiconductor wafer;
- storing in said non-volatile memory overlay measurements, the overlay measurements being determined from deviations measured between overlay marks of the semiconductor wafer, by means of an overlay measurement tool after the lithography step;
- subtracting with said simulation processor from the stored overlay measurements the alignment corrections and the process control parameters to produce cleansed overlay measurement data;
- determining an alternative alignment model;
- calculating with said simulation processor, from the alternative alignment model, alternative alignment corrections and alternative process control parameters;
- adding with said simulation processor the alternative alignment corrections and the alternative process control parameters to the cleansed overlay measurement data to produce alternative overlay data, the alternative overlay data enabling testing of lithography overlay;
- calculating with said simulation processor from the alternative overlay data updated alternative process corrections for a next lithography step;
- and
- using the updated alternative process corrections with the exposure tool for aligning and exposing portions of a further surface of a further one of the semiconductor wafer for projecting a pattern thereon.
A manufacturing control apparatus for controlling an exposure tool for projecting a pattern onto a surface of a semiconductor wafer by testing lithography overlay on a surface of a semiconductor wafer comprising:
- a non-volatile data store for storing alignment corrections, resulting from aligning, by means of an exposure tool, the surface of a semiconductor wafer with a light source and a projection optic prior to a lithography step, process control parameters, provided by an exposure controller and used, in addition to alignment corrections, by the exposure tool during the lithography step, and measured overlay data, the overlay data being determined from deviations measured between overlay marks of the semiconductor wafer by means of an overlay measurement tool;
- and
- a simulation processor for determining an alternative alignment model and calculating, from the alternative alignment model, alternative alignment corrections and alternative process control parameters, wherein the simulation processor is further configured to subtract the stored alignment corrections and the stored process control parameters from the stored measured overlay data to obtain cleansed overlay data and subsequently to add the alternative alignment corrections and the alternative process control parameters to the cleansed overlay data to obtain alternative overlay measurement data, enabling testing of lithography overlay and being usable to calculate updated alternative process corrections for a next lithography step,
- wherein the apparatus is connectable to the exposure tool, the exposure tool being adapted to use the updated alternative process corrections for aligning and exposing portions of a further surface of a further one of the semiconductor wafer for projecting a pattern thereon.
Dependencies are inferred from the claim text.