Real-time capture of traffic upon failure for protocol debug
AssigneeAdvantest Corporation
InventorDuane Champoux
Life of this patent
Estimating the term…
Abstract
An automated test equipment for simultaneous testing of multiple devices includes a traffic capture circuit configured to capture communications with a device under test, a capture memory configured to store the communications captured by the traffic capture circuit, and a routing logic configured to read the communications from the capture memory, e.g., random access memory (RAM). There may be one of each of the traffic capture circuit, the capture RAM, and the routing logic for each device of the multiple devices.
Claims19
An automated test equipment for simultaneous testing of multiple devices, comprising:
- a traffic capture circuit configured to capture all communications with a device under test;
- a capture memory configured to store said all communications captured by said traffic capture circuit;
- a routing logic configured to read said communications from said capture memory;
- and
- tester logic operable to generate meta data of communications that are not sent to the device under test.
An automated test equipment (ATE) apparatus comprising:
- a computer system comprising a system controller, said system controller communicatively coupled to a tester processor, wherein said system controller is operable to transmit instructions to said tester processor, and wherein said tester processor is operable to generate commands and data from said instructions for coordinating testing of a plurality of devices under test (DUTs);
- a plurality of field-programmable gate array (FPGA) components communicatively coupled to said tester processor via a bus, wherein each of said plurality of FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from said tester processor for testing a respective DUT of a plurality of DUTs;
- a plurality of downstream ports, each for communicating with a respective DUT and each communicatively coupled to a respective FPGA of said plurality of FPGAs,
- wherein each said downstream port further comprises:
- a traffic capture circuit configured to capture all communications with said respective device under test;
- a capture random access memory (RAM) configured to store said all communications captured by said traffic capture circuit;
- tester logic operable to generate meta data of communications that are not sent to and are not received from the DUT;
- and
- a routing logic configured to read said communications from said capture RAM.
A method comprising:
- generating meta data of communications that are not sent to and are not received from a device under test;
- capturing said meta data and all communications between a test system and the device under test to form captured communications;
- storing said captured communications into a capture memory that is part of said test system;
- responsive to a testing failure of the device under test, ceasing said storing;
- responsive to said testing failure, reading said captured communications from said capture memory to a failure analysis function of a computer system;
- analyzing the captured communications to determine a failure type;
- and
- generating a human readable report listing a failure type of the testing failure.
Dependencies are inferred from the claim text.