Rotorcraft with redundant processors using state comparison

A method of flying a rotorcraft, the method comprising:

• sensing a pilot input condition;
• sensing a flight condition of the rotorcraft;
• inputting the pilot input condition and the flight condition to a first hardware/software combination;
• determining, using the first hardware/software combination, a first control law state based on the pilot input condition and the flight condition;
• inputting the pilot input condition and the flight condition to a second hardware/software combination;
• determining, using the second hardware/software combination, a second control law state;
• comparing the first control law state and the second control law state;
• adopting the first control law state, in response to determining that the first control law state and the second control law state match;
• maintaining the first control law state, in response to determining that the first control law state and the second control law state match, when the first control law state is the same as an immediately previously adopted control law state;
• and
• maintaining a previous control law state and maintaining a current flight trim condition in response to determining the first control law state and the second control law state do not match.

A computer architecture for controlling a system, the computer architecture, including:

• a first processing lane, the first processing lane including a first microprocessor and a second microprocessor, wherein the first microprocessor and the second microprocessor have at least one material difference, which at least one material difference may cause, in the absence of an error, a different output from the second microprocessor relative to the output from the first microprocessor when the second microprocessor and the first microprocessor receive identical input data and run identical program steps on the identical input data;
• input ports configured to receive input data indicative of a condition of the system;
• a second processing lane, the second processing lane including a third microprocessor and a fourth microprocessor, wherein the third microprocessor and the fourth microprocessor are similar in all material respects, such that, absent an error, the fourth microprocessor and the third microprocessor will output a same result when the fourth microprocessor and the third microprocessor receive identical input data and run identical program steps on the identical data;
• a comparator configured to compare an output from the first microprocessor and the second microprocessor;
• and
• a state selector configured to select or maintain a state represented by the output from the first microprocessor when the output from the first microprocessor and the second microprocessor match and to maintain a current state when the output from the first microprocessor and the second microprocessor do not match.