# US 10,375,838 B2 · Sleeved coaxial printed circuit board vias > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,375,838 B2 - Document ID: US10375838B2 - Status: Granted - Kind: B2 - Application number: 15/459,383 - Filed: 2017-03-15 - Published: 2017-07-20 - Granted: 2019-08-06 - Earliest claimed: 2013-07-15 - Assignees: Massachusetts Institute of Technology - Applicants: Massachusetts Institute of Technology - Inventors: Glenn A. Brigham; Richard J. Stanley; Bradley Thomas Perry; Patrick J. Bell - Web page: https://patentgrep.com/patent/US10375838B2 ## CPC - H05K 3/42: Plated through-holes {or plated via connections} - H05K 1/0222: {for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence} - H05K 1/115: {Via connections; Lands around holes or via connections (H05K1/112 takes precedence)} - H05K 1/116: {Lands, clearance holes or other lay-out details concerning the surrounding of a via} - H05K 3/0094: {Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement} - H05K 3/4685: {Manufacturing of cross-over conductors} - H05K 2201/0959: Plated through-holes or plated blind vias filled with insulating material - H05K 2201/09745: Recess in conductor, e.g. in pad or in metallic substrate - H05K 2201/10242: Metallic cylinders - H05K 2203/03: Metal processing - H05K 2203/0703: Plating - H05K 2203/30: Details of processes not otherwise provided for in H05K2203/01 - H05K2203/17 - Y10T 29/49123: Co-axial cable - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ## Abstract A printed circuit board, and a method of fabricating the printed circuit board is disclosed. The printed circuit board includes at least one coaxial via. A hollow via is disposed in the printed circuit board. A metal sleeve is formed around the circumference of said hollow via. An inner conductive path is disposed in the hollow via. Additionally, an insulating material is disposed in the hollow via, between the conducting path and the metal sleeve. The conductive path is used to connect signal traces disposed on two different layers of the printed circuit board. In some embodiments, these signal traces carry signals having a frequency above 1 GHz, although the disclosure is not limited to this embodiment. ## Claims ### Claim 1 A method of manufacturing a sleeved coaxial via in a printed circuit board, comprising: affixing a plurality of layers together, one on top of another, to form the printed circuit board; drilling a first hole through said plurality of layers; plating an inner circumference of said first hole with a conductive material to create a metal sleeve; depositing an insulating material in said first hole after said plating, wherein said insulating material fills the first hole and is disposed at a top surface and a bottom surface of said printed circuit board; plating an entirety of said top surface, an entirety of said bottom surface and said insulating material disposed at said top surface and said bottom surface; drilling a second hole through said insulating material after said insulating material has been plated; inserting a conductive material in said second hole to form a conductive path; electrically connecting the metal sleeve to ground; and electrically connecting a signal trace on an outer layer of said printed circuit board to said conductive path, wherein the outer layer comprises said top surface or said bottom surface. ### Claim 2 (depends on 1) The method of claim 1, further comprising notching said metal sleeve near said outer layer after said plating. ### Claim 3 (depends on 2) The method of claim 2, wherein said notching comprises using a chemical, mechanical or electrical material removal process or a selective material removal process to create a notch in said metal sleeve. ### Claim 4 (depends on 1) The method of claim 1, wherein said outer layer comprises a plurality of traces, and said plurality of traces are created on said outer layer after said inserting. ### Claim 5 (depends on 1) The method of claim 1, wherein said first hole and said second hole are concentric. ### Claim 6 (depends on 1) The method of claim 1, further comprising electrically connecting a second signal trace on a second outer layer of said printed circuit board to said conductive path. ### Claim 7 (depends on 6) The method of claim 6, further comprising notching said metal sleeve near said second outer layer prior to said inserting. ### Claim 8 (depends on 1) The method of claim 1, wherein a ratio of a diameter of the first hole to a diameter of the second hole and a dielectric constant of the insulating material are selected to match an impedance of the sleeved coaxial via and the signal trace. ### Claim 9 (depends on 1) The method of claim 1, wherein a ratio of a diameter of the first hole to a diameter of the second hole and a dielectric constant of the insulating material are selected such that an impedance of the sleeved coaxial via matches a desired characteristic impedance. ### Claim 10 (depends on 1) The method of claim 1, wherein said insulating material is planarized after the depositing and before the plating so as to be at approximately the same level as the top surface and the bottom surface. ### Claim 11 (depends on 1) The method of claim 1, wherein said electrically connecting comprises etching said plating on said outer layer and on said insulating material to form said signal trace. ### Claim 12 (depends on 1) The method of claim 1, wherein said outer layer comprises said signal trace and said plating serves to electrically connect said signal trace to said conductive path.