# US 10,375,832 B2 · Method of forming an interference shield on a substrate

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- Number: US 10,375,832 B2
- Document ID: US10375832B2
- Status: Granted
- Kind: B2
- Application number: 14/956,214
- Filed: 2015-12-01
- Published: 2016-03-24
- Granted: 2019-08-06
- Earliest claimed: 2014-03-27
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Digvijay A. Raorane; Kemal Aygun; Daniel N. Sobieski; Drew W. Delaney
- Web page: https://patentgrep.com/patent/US10375832B2

## CPC

- H05K 3/007: {Manufacture or processing of a substrate for a printed circuit board supported by a temporary or sacrificial carrier (H05K1/187, H05K3/20 and H05K3/4682 take precedence)}
- C23C 14/14: Metallic material, boron or silicon
- H05K 1/0219: {Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors}
- H05K 1/185: associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
- H05K 3/02: in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K 3/30: Assembling printed circuits with electric components, e.g. with resistors
- H05K 3/4682: {Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H05K 2201/0715: provided by an outer layer of PCB
- H05K 2203/1469: Circuit made after mounting or encapsulation of the components
- H05K 2203/308: Sacrificial means, e.g. for temporarily filling a space for making a via or a cavity or for making rigid-flexible PCBs
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/10: characterised by their shape or disposition
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An apparatus including a die including a device side with contact points and lateral sidewalls defining a thickness of the die; a build-up carrier coupled to the die, the build-up carrier including a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die; and an interference shield including a conductive material disposed on the die and a portion of the build-up carrier. The apparatus may be connected to a printed circuit board. A method including forming a build-up carrier adjacent a device side of a die including a plurality of alternating layers of patterned conductive material and insulating material; and forming a interference shield on a portion of the build-up carrier.

## Claims

### Claim 1

A method of forming an interference shield on a substrate, the method comprising:
providing a die comprising contact points;
forming a build-up carrier adjacent a device side of the die, the build-up carrier comprising a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die, wherein the die is embedded in the build-up carrier, wherein forming the build-up carrier comprises forming the plurality of alternating layers of conductive material and dielectric material on a sacrificial panel, and after forming the plurality of alternating layers of conductive material and dielectric material, separating the build-up carrier from the sacrificial panel; and
forming an interference shield on a top and sidewalls of the build-up carrier, wherein the portion of the interference shield on the top of the build-up carrier is non-planar.

### Claim 2 (depends on 1)

The method of claim 1, wherein the interference shield is formed on a surface of the build-up carrier adjacent a backside of the die.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming the interference shield comprises sputtering a target material.

### Claim 4 (depends on 2)

The method of claim 2, wherein the interference shield comprises a plurality of layers of different conductive materials.

### Claim 5 (depends on 4)

The method of claim 4, wherein the plurality of different conductive materials comprise copper and nickel.

### Claim 6 (depends on 1)

The method of claim 1, wherein the sacrificial panel comprises a conductive material layer having a cavity therein and prior to forming the plurality of alternating layers of conductive material and dielectric material, the method comprises placing the die in the cavity and separating the build-up carrier from the sacrificial panel comprises removing the conductive material layer having the cavity.

### Claim 7 (depends on 1)

The method of claim 1, wherein at least one layer of the layers of patterned conductive material contacts the interference shield.

### Claim 8 (depends on 7)

The method of claim 7, wherein the at least one layer of the layers of patterned conductive material extends laterally to a width of the build-up carrier such that the at least one layer is exposed at least one side portion of opposing side portions of the build-up carrier and forming the interference shield comprises forming the interference shield on the at least one side portion.

### Claim 9 (depends on 7)

The method of claim 7, wherein the at least one layer of the layers of patterned conductive material defines a ground plane.

### Claim 10 (depends on 1)

The method of claim 1, wherein a layer of the layers of patterned conductive material is in direct electrical contact with the interference shield.

### Claim 11

A method of forming an interference shield on a substrate, the method comprising:
providing a die comprising contact points;
forming a build-up carrier adjacent a device side of the die, the build-up carrier comprising a plurality of alternating layers of patterned conductive material and insulating material, wherein at least one of the layers of patterned conductive material is coupled to one of the contact points of the die, wherein forming the build-up carrier comprises forming the plurality of alternating layers of conductive material and dielectric material on a sacrificial panel and after forming the plurality of alternating layers of conductive material and dielectric material, separating the build-up carrier from the sacrificial panel; and
forming an interference shield on a portion of the build-up carrier, wherein the interference shield is formed on a surface of the build-up carrier adjacent a backside of the die, wherein forming the interference shield comprises sputtering a target material, and wherein the plurality of different conductive materials comprise copper and nickel.

### Claim 12 (depends on 11)

The method of claim 11, wherein the sacrificial panel comprises a conductive material layer having a cavity therein and prior to forming the plurality of alternating layers of conductive material and dielectric material, the method comprises placing the die in the cavity and separating the build-up carrier from the sacrificial panel comprises removing the conductive material layer having the cavity.