# US 10,375,823 B2 · Differential signal traces including a solder mask disposed thereon > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,375,823 B2 - Document ID: US10375823B2 - Status: Granted - Kind: B2 - Application number: 15/578,574 - Filed: 2016-06-01 - Published: 2018-05-17 - Granted: 2019-08-06 - Earliest claimed: 2015-06-03 - Assignees: Fci USA LLC - Applicants: Fci USA LLC - Inventors: Benjamin Reed Staudt - Web page: https://patentgrep.com/patent/US10375823B2 ## CPC - H05K 1/0245: {Lay-out of balanced signal pairs, e.g. differential lines or twisted lines} - H01P 3/081: {Microstriplines} - H01P 11/003: {Manufacturing lines with conductors on a substrate, e.g. strip lines, slot lines} - H05K 1/0248: {Skew reduction or using delay lines} - H05K 3/10: in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern - H05K 3/28: Applying non-metallic protective coatings {(H05K3/0091 takes precedence; methods for intermediate insulating layers for build-up multilayer circuits H05K3/4673)} - H10W 70/65: Shapes or dispositions of interconnections - H10W 70/69: Insulating materials thereof - H05K 3/3452: Solder masks - H05K 2201/0989: Coating free areas, e.g. areas other than pads or lands free of solder resist - H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS - H01P: WAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE (operating at optical frequencies G02B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Disclosed herein is a method. A first electrically conductive trace is provided on a substrate. A second electrically conductive trace is providing on the substrate proximate the first electrically conductive trace. A solder mask is provided at the first and the second electrically conductive traces. A portion of the first electrically conductive trace is free of any portion of the solder mask covering thereon. ## Claims ### Claim 1 A method comprising: providing a first electrically conductive trace on a substrate; providing a second electrically conductive trace on the substrate proximate the first electrically conductive trace; and providing a solder mask at the first and the second electrically conductive traces, wherein a portion of the first electrically conductive trace is free of any portion of the solder mask covering thereon and wherein: the providing of the solder mask further comprises covering the first and the second electrically conductive traces including the portion of the first electrically conductive trace and subsequently removing the solder mask from the portion of the first electrically conductive trace. ### Claim 2 (depends on 1) A method as in claim 1 wherein the first electrically conductive trace and the second electrically conductive trace each comprise a bend or turn. ### Claim 3 (depends on 2) A method as in claim 2 wherein the portion of the first electrically conductive trace free of any portion of the solder mask is disposed at the bend of the first electrically conductive trace. ### Claim 4 (depends on 1) A method as in claim 1 wherein the first electrically conductive trace comprises a longer length than the second electrically conductive trace. ### Claim 5 (depends on 1) A method as in claim 1 wherein, after removing the solder mask, the portion of the first electrically conductive trace comprises a first dielectric different than the solder mask over the portion and wherein the second electrically conductive trace comprises the solder mask comprising a second different dielectric over the second electrically conductive trace. ### Claim 6 (depends on 5) A method as in claim 5 wherein the first dielectric is an air void. ### Claim 7 (depends on 1) A method as in claim 1 wherein the first and the second electrically conductive traces are differential pair traces configured for differential signaling. ### Claim 8 (depends on 1) A method as in claim 1 wherein the substrate is a printed circuit board substrate. ### Claim 9 A printed circuit board comprising: a substrate; a first electrically conductive trace on the substrate; a second electrically conductive trace on the substrate proximate the first electrically conductive trace; and a solder mask at the first and the second electrically conductive traces, wherein the solder mask covers a length of the second electrically conductive trace, and wherein the solder mask does not cover an adjacent length of the first electrically conductive trace, and wherein the solder mask covers a majority of the first and the second electrically conductive traces. ### Claim 10 (depends on 9) A printed circuit board as in claim 9 wherein the printed circuit board is configured such that an electrical signal can travel faster along the adjacent length of the first electrically conductive trace than the length of the second electrically conductive trace. ### Claim 11 (depends on 9) A printed circuit board as in claim 9 wherein a dielectric identical to the solder mask covers the length of the second electrically conductive trace, and wherein a dielectric different than the solder mask covers the adjacent length of the first electrically conductive trace. ### Claim 12 (depends on 9) A printed circuit board as in claim 9 wherein an air void covers the adjacent length of the first electrically conductive trace. ### Claim 13 (depends on 9) A printed circuit board as in claim 9 wherein the adjacent length of the first electrically conductive trace comprises a longer physical length than the physical length of the second electrically conductive trace. ### Claim 14 (depends on 13) A printed circuit board as in claim 13 wherein the first electrically conductive trace and the second electrically conductive trace comprise substantially equal effective electrical lengths. ### Claim 15 (depends on 9) A printed circuit board as in claim 9 wherein the first and the second electrically conductive traces are differential pair traces configured for differential signaling. ### Claim 16 (depends on 15) A printed circuit board as in claim 15 wherein the printed circuit board is configured to reduce skew between the differential pair traces. ### Claim 17 (depends on 9) A printed circuit board as in claim 9 wherein the first electrically conductive trace and the second electrically conductive trace are substantially parallel to each other. ### Claim 18 (depends on 9) A printed circuit board as in claim 9 wherein the first electrically conductive trace and the second electrically conductive trace each comprise a bend or turn. ### Claim 19 A method comprising: providing a first electrically conductive trace on a substrate; providing a second electrically conductive trace on the substrate proximate the first electrically conductive trace; and providing a solder mask at the first and the second electrically conductive traces, wherein a portion of the first electrically conductive trace is free of any portion of the solder mask covering thereon and wherein: the providing of the solder mask further comprises temporarily masking the portion of the first electrically conductive trace when the solder mask is applied over the substrate. ### Claim 20 (depends on 19) A method as in claim 19 wherein, after temporarily masking the portion of the first electrically conductive trace, the portion of the first electrically conductive trace comprises a first dielectric different than the solder mask over the portion and wherein the second electrically conductive trace comprises the solder mask comprising a second different dielectric over the second electrically conductive trace. ### Claim 21 (depends on 20) A method as in claim 20 wherein the first dielectric is an air void. ### Claim 22 (depends on 19) A method as in claim 19 wherein the first electrically conductive trace comprises a longer length than the second electrically conductive trace. ### Claim 23 (depends on 19) A method as in claim 19 wherein the first electrically conductive trace and the second electrically conductive trace each comprise a bend or turn. ### Claim 24 (depends on 23) A method as in claim 23 wherein the portion of the first electrically conductive trace free of any portion of the solder mask is disposed at the bend of the first electrically conductive trace. ### Claim 25 (depends on 19) A method as in claim 19 wherein the substrate is a printed circuit board substrate. ### Claim 26 (depends on 19) A method as in claim 19 wherein the first and the second electrically conductive traces are differential pair traces configured for differential signaling.