# US 10,375,633 B2 · System and method for providing power savings in an access point via ethernet rate and interface shifting

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- Number: US 10,375,633 B2
- Document ID: US10375633B2
- Status: Granted
- Kind: B2
- Application number: 15/374,572
- Filed: 2016-12-09
- Published: 2018-06-14
- Granted: 2019-08-06
- Earliest claimed: 2016-12-09
- Assignees: Cisco Technology, Inc.
- Applicants: Cisco Technology, Inc.
- Inventors: Clark Carty; Daniel Duckworth; Mark Pleso
- Web page: https://patentgrep.com/patent/US10375633B2

## CPC

- H04W 52/0212: {managed by the network, e.g. network or access point is leader and terminal is follower}
- H04W 52/0206: {in access points, e.g. base stations}
- H04W 88/08: Access point devices
- Y02D 30/70: in wireless communication networks
- H04W: WIRELESS COMMUNICATION NETWORKS (broadcast communication H04H; communication systems using wireless links for non-selective communication, e.g. wireless extensions H04M1/72)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

Disclosed is a method for managing bus channels between a physical layer and a media access channel layer of a network. The method includes determining a current rate of link speed on a media dependent interface side of a physical layer of a network architecture. When the current rate changes to yield a new link speed, the method includes determining a minimal (or near minimal) bus size required to implement the new link speed and switching to the minimal bus size between a physical coding sublayer of the physical layer and a reconciliation sublayer of a datalink layer of the network architecture. The method further includes switching to the minimal bus size between a physical coding sublayer of the physical layer and a reconciliation sublayer of a datalink layer of the network architecture.

## Claims

### Claim 1

A method for directing network traffic over a plurality of buses, each bus accommodating a corresponding maximum particular link speed, the method comprising:
determining a current rate of link speed on a media dependent interface side of a physical layer of a network architecture;
when the current rate changes to yield a new link speed, determining a minimal bus size required to implement the new link speed;
selecting a bus from the plurality of buses that is (a) available and (b) has a lowest corresponding maximum speed that will accommodate the determined minimal bus size; and
switching to the selected bus between a physical coding sublayer of the physical layer and a reconciliation sublayer of a datalink layer of the network architecture;
wherein determining the minimal bus size further comprises performing a lookup in a matrix that comprises data regarding a correlation between link speed and an order of a relative power draw between available buses.

### Claim 2 (depends on 1)

The method of claim 1, wherein the minimal bus size comprises a SerDes lane.

### Claim 3 (depends on 1)

The method of claim 1, wherein the minimal bus size comprises a plurality of SerDes lanes.

### Claim 4 (depends on 1)

The method of claim 1, wherein the plurality of buses comprise one or more of SGMII, 2500BASE-X, and RXAUI.

### Claim 5 (depends on 1)

The method of claim 1, wherein determining the minimal bus size further comprises determining a minimal speed for the minimal bus size required to implement the new link speed.

### Claim 6 (depends on 1)

The method of claim 1, wherein the minimal bus size comprises a bus size relatively smaller than other available bus sizes.

### Claim 7

A system for directing network traffic over a plurality of buses, each bus accommodating a corresponding maximum particular link speed, the system comprising:
a processor; and
a computer-readable storage device storing instructions which, when executed by the processor, cause the processor to perform operations comprising:
determining a current rate of link speed on a media dependent interface side of a physical layer of a network architecture;
when the current rate changes to yield a new link speed, determining a minimal bus size required to implement the new link speed;
selecting a bus from the plurality of buses that is (a) available and (b) has a lowest corresponding maximum speed that will accommodate the determined minimal bus size; and
switching to the selected bus between a physical coding sublayer of the physical layer and a reconciliation sublayer of a datalink layer of the network architecture;
wherein determining the minimal bus size further comprises performing a lookup in a matrix that comprises data regarding a correlation between link speed and an order of a relative power draw between available buses.

### Claim 8 (depends on 7)

The system of claim 7, wherein the minimal bus size comprises one of a SerDes lane or a plurality of SerDes lanes.

### Claim 9 (depends on 7)

The system of claim 7, wherein the plurality of buses comprise SGMII, 2500BASE-X, and RXAUI.

### Claim 10 (depends on 7)

The system of claim 7, wherein determining the minimal bus size further comprises determining a minimal speed for the minimal bus size required to implement the new link speed.

### Claim 11 (depends on 7)

The system of claim 7, wherein the minimal bus size comprises a bus size relatively smaller than other available bus sizes.

### Claim 12

A non-transitory computer-readable storage device storing instructions for directing network traffic over a plurality of buses, each bus accommodating a corresponding maximum particular link speed, the instructions when executed by a processor cause the processor to perform operations comprising:
determining a current rate of link speed on a media dependent interface side of a physical layer of a network architecture;
when the current rate changes to yield a new link speed, determining a minimal bus size required to implement the new link speed;
selecting a bus from the plurality of buses that is (a) available and (b) has a lowest corresponding maximum speed that will accommodate the determined minimal bus size; and
switching to the selected bus between a physical coding sublayer of the physical layer and a reconciliation sublayer of a datalink layer of the network architecture;
wherein determining the minimal bus size further comprises performing a lookup in a matrix that comprises data regarding a correlation between link speed and an order of a relative power draw between available buses.

### Claim 13 (depends on 12)

The non-transitory computer-readable storage device of claim 12, wherein the minimal bus size comprises one of a SerDes lane or a plurality of SerDes lanes.

### Claim 14 (depends on 12)

The non-transitory computer-readable storage device of claim 12, wherein the plurality of buses comprise one or more of SGMII, 2500BASE-X, and RXAUI.

### Claim 15 (depends on 12)

The non-transitory computer-readable storage device of claim 12, wherein determining the minimal bus size further comprises determining a minimal speed for the minimal bus size required to implement the new link speed.

### Claim 16 (depends on 12)

The non-transitory computer-readable storage device of claim 12, wherein the minimal bus size comprises a bus size relatively smaller than other available bus sizes.