# US 10,375,336 B2 · Methods and apparatus for a track and hold amplifier

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- Number: US 10,375,336 B2
- Document ID: US10375336B2
- Status: Granted
- Kind: B2
- Application number: 15/666,781
- Filed: 2017-08-02
- Published: 2019-02-07
- Granted: 2019-08-06
- Earliest claimed: 2017-08-02
- Assignees: Semiconductor Components Industries, LLC
- Applicants: Semiconductor Components Industries, LLC
- Inventors: Shankar Ramakrishnan
- Web page: https://patentgrep.com/patent/US10375336B2

## CPC

- H04N 25/778: comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself
- G11C 27/026: {associated with an amplifier (G11C27/028 takes precedence)}
- H03F 1/223: {with MOSFET's}
- H03F 1/34: Negative-feedback-circuit arrangements with or without positive feedback (H03F1/02 - H03F1/30, H03F1/38 - H03F1/50, H03F3/50 take precedence {; for rejection of common mode signals H03F3/45479})
- H03F 3/72: Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03G 1/0094: {using switched capacitors}
- H03K 5/08: by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding (H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30)
- H04N 25/00: Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N 25/618: for random or high-frequency noise
- H04N 25/78: Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
- H03F 2203/7221: the gated amplifier being switched on or off by a switch at the output of the amplifier
- H03M 1/1245: {Details of sampling arrangements or methods}
- H04N: PICTORIAL COMMUNICATION, e.g. TELEVISION
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03F: AMPLIFIERS
- H03G: CONTROL OF AMPLIFICATION
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

Various embodiments of the present technology may comprise methods and apparatus for a track-and-hold amplifier configured to sample and amplify an analog signal. Methods and apparatus for a track-and-hold amplifier according to various aspects of the present invention may comprise an isolation circuit configured to isolate transient current in a track-and-hold capacitor during a track phase. According to various embodiments, selective activation of the isolation circuit provides a settling time that is independent of the gain of the amplifier.

## Claims

### Claim 1

A track-and-hold amplifier circuit configured to be coupled to a supply voltage and a first reference voltage and receive an input signal, comprising:
a gain setting element coupled to the input signal;
a cascode circuit coupled to the gain setting element;
a track-and-hold capacitor comprising:
a first capacitor terminal coupled to the gain setting element at a first node; and
a second capacitor terminal; and
an isolation circuit, coupled to the second capacitor terminal of the track-and-hold capacitor and the cascode circuit, and configured to selectively isolate transient current in the track-and-hold capacitor and redirect the transient current through at least a portion of the cascode circuit,
wherein the isolation circuit comprises:
a third transistor comprising:
a first terminal; and
a second terminal;
wherein:
the first terminal is directly coupled to the second capacitor terminal at a third node; and
the second terminal is directly coupled to the cascode circuit.

### Claim 2 (depends on 1)

The track-and-hold amplifier according to claim 1, further comprising a first current source, wherein the first current source is:
coupled to the cascode circuit and the gain setting element at the first node; and
selectively coupled to the track-and-hold capacitor.

### Claim 3 (depends on 1)

The track-and-hold amplifier according to claim 1, wherein the isolation circuit further comprises:
a second current source coupled to the third node; and
a switch coupled between the second terminal and the first reference voltage.

### Claim 4 (depends on 3)

The track-and-hold amplifier according to claim 3, wherein:
the third transistor further comprises a third terminal coupled to a dynamic voltage;
the second terminal is coupled to the cascode circuit via a fourth node.

### Claim 5 (depends on 3)

The track-and-hold amplifier according to claim 3, wherein the switch selectively couples the second terminal:
to the first reference voltage during a hold phase; and
to the cascode circuit via a fourth node during a track phase.

### Claim 6 (depends on 1)

The track-and-hold amplifier according to claim 1, wherein:
the cascode circuit comprises:
a first transistor; and
a second transistor;
wherein a fourth node is positioned between the first and second transistors; and
the isolation circuit comprises a clamp device coupled to the fourth node and the first reference voltage.

### Claim 7 (depends on 6)

The track-and-hold amplifier according to claim 6, wherein the clamp device has a clamping voltage that is greater than a drain-to-source voltage of the first transistor.

### Claim 8 (depends on 1)

The track-and-hold amplifier according to claim 1, wherein the gain setting element comprises:
a first impedance element coupled in series with a second impedance element; and
a second node positioned between the first and second impedance elements;
wherein:
each impedance element may comprise at least one of a resistor and a capacitor; and
a series capacitance value of the first and second impedance elements is less than a capacitance value of the track-and-hold capacitor.

### Claim 9 (depends on 1)

The track-and-hold amplifier according to claim 1, wherein the cascode circuit is coupled to:
the gain setting element via a second node; and
a bias voltage.

### Claim 10 (depends on 1)

The track-and-hold amplifier according to claim 1, wherein the isolation circuit comprises a clamp device configured to provide a current path from the isolation circuit to the first reference voltage when at least a portion of the cascode circuit is off.

### Claim 11 (depends on 1)

The track-and-hold amplifier according to claim 1, further comprising:
a third current source;
a fourth transistor coupled to the third current source and a second reference voltage; and
a fifth transistor coupled to the third current source, the input signal, and the first reference voltage.

### Claim 12

A method for improving an output signal settling time for a track-and-hold amplifier, comprising:
during a tracking phase:
supplying a first current to a cascode circuit comprising a first transistor and a second transistor;
tracking an input signal at a first terminal of a track-and-hold capacitor;
supplying a second current to a third transistor coupled to a second terminal of the track-and-hold capacitor; and
directing a transient current through the track-and-hold capacitor to a reference voltage through one of: the first transistor and a clamp device;
during a holding phase:
selectively coupling the third transistor to the reference voltage;
stopping the first current; and
supplying a dynamic voltage to the third transistor.

### Claim 13

An imaging system, comprising:
a plurality of pixel columns;
a plurality of track-and-hold amplifiers, wherein:
each pixel column is coupled to one track-and-hold amplifier; and
each track-and-hold amplifier comprises:
a gain setting element coupled to the input signal;
a cascode circuit, coupled to the gain setting element at a second node and a bias voltage, comprising:
a first transistor; and
a second transistor;
a track-and-hold capacitor, comprising:
a first terminal; and
a second terminal;
a first current source, coupled to the cascode circuit and the gain setting element at a first node, and selectively coupled to the track-and-hold capacitor;
a third transistor, comprising:
a first terminal;
a second terminal; and
a third terminal;
wherein:
the first terminal of the third transistor is coupled to the second terminal of the track-and-hold capacitor at a third node;
the second terminal of the third transistor is coupled to the cascode circuit at a fourth node; and
the third terminal of the third transistor is coupled to a dynamic voltage;
a switch coupled between the second terminal of the third transistor and a reference voltage; and
a second current source coupled to the third node.

### Claim 14 (depends on 13)

The imaging system according to claim 13, wherein the switch selectively couples the second terminal of the third transistor:
to the reference voltage during a hold phase; and
to the cascode circuit via a fourth node during a track phase.

### Claim 15 (depends on 13)

The imaging system according to claim 13, wherein the gain setting element comprises:
a first impedance element coupled in series with a second impedance element; and
a second node positioned between the first and second impedance elements;
wherein:
each impedance element may comprise at least one of a resistor and a capacitor; and
a series capacitance value of the first and second impedance elements is less than a capacitance value of the track-and-hold capacitor.

### Claim 16 (depends on 13)

The imaging system according to claim 13, further comprising a ramp analog-digital converter (ADC) configured to receive an output signal from each track-and-hold amplifier, and wherein the dynamic voltage is a ramp voltage.

### Claim 17 (depends on 13)

The imaging system according to claim 13, further comprising a clamp device coupled between the fourth node and the reference voltage, wherein the clamp device has a clamping voltage that is greater than a drain-to-source voltage of the first transistor.

### Claim 18 (depends on 13)

The imaging system according to claim 13, further comprising a clamp device configured to provide a current path from the third transistor to the reference voltage when the first transistor is off.

### Claim 19 (depends on 13)

The imaging system according to claim 13, further comprising:
a third current source;
a fourth transistor coupled to the third current source and a reference voltage; and
a fifth transistor coupled to the third current source.