# US 10,375,038 B2 · Symmetric multiprocessing management > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,375,038 B2 - Document ID: US10375038B2 - Status: Granted - Kind: B2 - Application number: 15/364,297 - Filed: 2016-11-30 - Published: 2018-05-31 - Granted: 2019-08-06 - Earliest claimed: 2016-11-30 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Deepak Kodihalli; Venkatesh Sainath; Dhruvaraj Subhashchandran - Web page: https://patentgrep.com/patent/US10375038B2 ## CPC - H04L 63/0435: {wherein the sending and receiving network entities apply symmetric encryption, i.e. same key used for encryption and decryption (cryptographic mechanisms or cryptographic arrangements for symmetric key encryption H04L9/06)} - G06F 11/00: Error detection; Error correction; Monitoring (error detection, correction or monitoring in information storage based on relative movement between record carrier and transducer G11B20/18; monitoring, i.e. supervising the progress of recording or reproducing G11B27/36; in static stores G11C29/00) - G06F 11/1423: {by reconfiguration of paths} - G06F 11/16: Error detection or correction of the data by redundancy in hardware - G06F 11/3006: {where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems (multiprogramming arrangements G06F9/46; allocation of resources G06F9/50)} - G06F 11/3024: {where the computing system component is a central processing unit [CPU]} - G06F 11/3048: {where the topology of the computing system or computing system component explicitly influences the monitoring activity, e.g. serial, hierarchical systems} - G06F 11/3051: {Monitoring arrangements for monitoring the configuration of the computing system or of the computing system component, e.g. monitoring the presence of processing resources, peripherals, I/O links, software programs (verification or detection of system hardware configuration G06F11/2247)} - H04L 63/061: {for key exchange, e.g. in peer-to-peer networks (cryptographic mechanisms or cryptographic arrangements for key agreement H04L9/0838)} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Disclosed aspects relate to symmetric multiprocessing (SMP) management. A first SMP topology may be identified by a service processor firmware. The first SMP topology may indicate a first set of connection paths for a plurality of processor chips of a multi-node server. A second SMP topology may be identified by the service processor firmware. The second SMP topology may indicate a second set of connection paths for the plurality of processor chips of the multi-node server. The second SMP topology may differ from the first SMP topology. An error event related to the first SMP topology may be detected. A set of traffic may be routed using the second SMP topology. The set of traffic may be routed by the service processor firmware in response to detecting the error event related to the first SMP topology. ## Claims ### Claim 1 A computer-implemented method of symmetric multiprocessing (SMP) management with respect to a multi-node server by service processor firmware of a hardware service processor, the method comprising: identifying, by the service processor firmware, a first SMP topology which indicates a first set of connection paths for a plurality of processor chips of the multi-node server; identifying, by the service processor firmware, a second SMP topology which indicates a second set of connection paths for the plurality of processor chips of the multi-node server, wherein the second SMP topology differs from the first SMP topology; detecting an error event related to the first SMP topology; routing, by the service processor firmware in response to detecting the error event related to the first SMP topology, a set of traffic using the second SMP topology, wherein the identifying the first SMP topology, the identifying the second SMP topology, the detecting, and the routing each occur in an automated fashion without user intervention; and detecting, with respect to the error event relate to the first SMP topology, a traffic flow error in the first set of connection paths. ### Claim 2 (depends on 1) The method of claim 1, further comprising: initiating an initial program load (IPL); and validating, by the service processor firmware, a potential for one or more SMP topologies. ### Claim 3 (depends on 1) The method of claim 1, further comprising: building, by writing connection path information in a set of registers which has a bus-based routing configuration, one or more SMP topologies. ### Claim 4 (depends on 1) The method of claim 1, further comprising: ascertaining, for a group of respective processor chips of a group of respective nodes of the multi-node server, a group of respective identifiers; establishing, to link like-identifiers using the group of respective identifiers, a plurality of inter-node connection paths across the group of respective nodes of the multi-node server; and establishing a plurality of intra-node connection paths for the group of respective nodes of the multi-node server. ### Claim 5 (depends on 1) The method of claim 1, further comprising: configuring the second SMP topology such that each entire connection path of the second set of connection paths has a difference from every entire connection path of the first set of connection paths indicated by the first SMP topology. ### Claim 6 (depends on 1) The method of claim 1, further comprising: switching, in a dynamic fashion in response to detecting the error event related to the first SMP topology, the set of traffic from utilizing the first set of connection paths indicated by the first SMP topology to utilizing the second set of connection paths indicated by the second SMP topology. ### Claim 7 (depends on 1) The method of claim 1, further comprising: detecting, with respect to the error event related to the first SMP topology, a cable error in the first set of connection paths. ### Claim 8 (depends on 1) The method of claim 1, further comprising: detecting, with respect to the error event related to the first SMP topology, a processor configuration error in the first set of connection paths. ### Claim 9 (depends on 1) The method of claim 1, further comprising: modifying, by service processor firmware with respect to routing of the set of traffic, a quantitative connection path characteristic. ### Claim 10 (depends on 1) The method of claim 1, further comprising: computing, in a dynamic fashion by the service processor firmware in response to detecting the error event related to the first SMP topology, the second SMP topology which indicates the second set of connection paths for the plurality of processor chips of the multi-node server. ### Claim 11 (depends on 1) The method of claim 1, further comprising: computing, by the service processor firmware based on a plurality of address ranges which map to the plurality of processor chips of the multi-node server, the second SMP topology which indicates the second set of connection paths for the plurality of processor chips of the multi-node server. ### Claim 12 (depends on 1) The method of claim 1, further comprising: computing, by the service processor firmware using a processor chip connector list and a set of registers, the second SMP topology which indicates the second set of connection paths for the plurality of processor chips of the multi-node server. ### Claim 13 (depends on 1) The method of claim 1, further comprising: constructing, by the service processor firmware using a set of registers having connection path information, a routing table for the plurality of processor chips of the multi-node server. ### Claim 14 (depends on 1) The method of claim 1, wherein the operational steps each occur in a dynamic fashion to streamline symmetric multiprocessing management. ### Claim 15 (depends on 1) The method of claim 1, further comprising: initiating an initial program load (IPL); validating, by the service processor firmware, a potential for one or more SMP topologies; building, by writing connection path information in a set of registers which has a bus-based routing configuration, one or more SMP topologies; ascertaining, for a group of respective processor chips of a group of respective nodes of the multi-node server, a group of respective identifiers; establishing, to link like-identifiers using the group of respective identifiers, a plurality of inter-node connection paths across the group of respective nodes of the multi-node server; establishing a plurality of intra-node connection paths for the group of respective nodes of the multi-node server; configuring the second SMP topology such that each entire connection path of the second set of connection paths has a difference from every entire connection path of the first set of connection paths indicated by the first SMP topology; detecting, with respect to the error event related to the first SMP topology, a traffic flow error in the first set of connection paths; and switching, in a dynamic fashion in response to detecting the error event related to the first SMP topology, the set of traffic from utilizing the first set of connection paths indicated by the first SMP topology to utilizing the second set of connection paths indicated by the second SMP topology. ### Claim 16 A system of symmetric multiprocessing (SMP) management with respect to a multi-node server by service processor firmware of a hardware service processor, the system comprising: a memory having a set of computer readable computer instructions, and a processor for executing the set of computer readable instructions, the set of computer readable instructions including: identifying, by the service processor firmware, a first SMP topology which indicates a first set of connection paths for a plurality of processor chips of the multi-node server; identifying, by the service processor firmware, a second SMP topology which indicates a second set of connection paths for the plurality of processor chips of the multi-node server, wherein the second SMP topology differs from the first SMP topology; detecting an error event related to the first SMP topology; routing, by the service processor firmware in response to detecting the error event related to the first SMP topology, a set of traffic using the second SMP topology, wherein the identifying the first SMP topology, the identifying the second SMP topology, the detecting, and the routing each occur in an automated fashion without user intervention; and detecting, with respect to the error event related to the first SMP topology, a traffic flow error in the first set of connection paths. ### Claim 17 A computer program product of symmetric multiprocessing (SMP) management with respect to a multi-node server by service processor firmware of a hardware service processor, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the computer readable storage medium is not a transitory signal per se, the program instructions executable by a processor to cause the processor to perform a method comprising: identifying, by the service processor firmware, a first SMP topology which indicates a first set of connection paths for a plurality of processor chips of the multi-node server; identifying, by the service processor firmware, a second SMP topology which indicates a second set of connection paths for the plurality of processor chips of the multi-node server, wherein the second SMP topology differs from the first SMP topology; detecting an error event related to the first SMP topology; routing, by the service processor firmware in response to detecting the error event related to the first SMP topology, a set of traffic using the second SMP topology, wherein the identifying the first SMP topology, the identifying the second SMP topology, the detecting, and the routing each occur in an automated fashion without user intervention; and detecting, with respect to the error event related to the first SMP topology, a traffic flow error in the first set of connection paths. ### Claim 18 (depends on 17) The computer program product of claim 17, wherein the program instructions are stored in the computer readable storage medium in a data processing system, and wherein the program instructions were downloaded over a network from a remote data processing system. ### Claim 19 (depends on 17) The computer program product of claim 17, wherein the program instructions are stored in the computer readable storage medium in a server data processing system, and wherein the program instructions are downloaded over a network to the remote data processing system for use in a second computer readable storage medium with the remote data processing system.