# US 10,374,852 B1 · Ka-band modulator and transmitter

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- Number: US 10,374,852 B1
- Document ID: US10374852B1
- Status: Granted
- Kind: B1
- Application number: 16/125,938
- Filed: 2018-09-10
- Granted: 2019-08-06
- Earliest claimed: 2018-09-10
- Assignees: United States of America as represented by the Administrator of NASA
- Applicants: The United States of America as represented by the Administrator of NASA
- Inventors: Wei-Chung Huang; Jeffrey M. Jaso
- Web page: https://patentgrep.com/patent/US10374852B1

## CPC

- H04L 27/2053: {using more than one carrier, e.g. carriers with different phases}
- H04B 7/18517: {Transmission equipment in earth stations}
- H04B 7/18582: {Arrangements for data linking, i.e. for data framing, for error recovery, for multiple access}
- H04L 1/0041: {Arrangements at the transmitter end}
- H04L 1/0058: {Block-coded modulation}
- H04L 7/0091: {Transmitter details}
- H04L 7/048: {using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal}
- H04L 25/03834: {using pulse shaping}
- H04L 27/2082: {for offset or staggered quadrature phase shift keying}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H04B: TRANSMISSION

## Abstract

The present invention relates to a high data rate Ka-band modulator and transmitter for space applications that functions on the entire NASA Space Network Return Link band of 25.25-27.75 GHz. The modulator is capable of quadrature phase-shift keying (QPSK) modulation and 8-PSK modulation. The transmitter can be designed to provide an adjustable drive to a traveling-wave tube amplifier (TWTA) or transmit power.

## Claims

### Claim 1

A Ka-band transmitter, comprising:
a first modulator including a field programmable gate array (FPGA), said FPGA including:
a serializer/deserializer (SerDes), which receives data in a data stream;
a buffer which buffers said data in said data stream from the serializer/deserializer;
a low-density parity check (LDPC) encoder which encodes said data in said data stream from the buffer with a 7/8 LDPC error-correcting code to result in a data stream of encoded symbols;
a randomizer which randomizes said encoded symbols in said data stream;
an in-phase/quadrature (I/Q) splitter which splits said randomized encoded symbols in said data stream into an I channel data stream and a Q channel data stream; and
a plurality of pulse shapers for each of said I channel data stream and said Q channel data stream, such that rates of said I channel data stream and said Q channel data stream of said encoded symbols below 400 Msps are digitally filtered with a root-raised cosine filter;
wherein resulting digitally filtered encoded symbols in said I channel data stream and said Q channel data stream are parallelized into 12-bit words which are each clocked exiting said FPGA;
a plurality of digital-to-analog converters (DACs) which receive said 12-bit words from said FPGA to form an I analog baseband signal and a Q analog baseband signal;
a tunable filter bank including a plurality of low-pass analog filters which filter said I analog baseband signal and said Q analog baseband signal;
a second harmonic vector modulator which receives said I analog baseband signal and said Q analog baseband signal from said tunable filter bank; and
a synthesizer including a local oscillator which pumps said second harmonic vector modulator to output a radio frequency (RF) signal;
wherein said RF signal is an Offset Quadrature Phase Shift Keying (OQPSK) modulated signal at a center frequency equal to: 2*fLo+fIF, where fIF is a total encoded symbol rate and fLo is a local oscillator frequency; and
wherein said RF signal is in a Ka-band frequency range including inside a Ka-band return link range of 25.25-27.75 GHz.

### Claim 2 (depends on 1)

The transmitter of claim 1, further comprising:
a first low-pass analog filter which receives output from said second harmonic vector modulator;
a first low-noise amplifier (LNA) which receives output from said first low-pass analog filter;
a variable-voltage attenuator (VVA) which attenuates said output from said first low-noise amplifier (LNA);
a second low-noise amplifier (LNA) which receives said attenuated output from said variable-voltage attenuator (VVA);
a second low-pass analog filter which receives output from said second low-noise amplifier (LNA);
a medium-power amplifier (MPA) which receives output from said second low-pass analog filter and emits a signal output; and
a microstrip-to-waveguide transition which receives said signal output from said medium-power amplifier (MPA) and converts said signal output to a waveguide signal output, to produce said radio frequency (RF) output.

### Claim 3 (depends on 2)

The transmitter of claim 2, further comprising:
a balanced power combiner disposed between said medium power amplifier (MPA) and said microstrip-to-waveguide transition, said balanced combiner which includes a 90-degrees phase shifter which splits output from said medium-power amplifier (MPA) evenly from said phase shifter into two power outputs and forwards said two power outputs to a waveguide hybrid coupler;
wherein said phase shifter and said waveguide hybrid coupler provide wideband phase and amplitude balance over said Ka-band return link range of 25.25-27.75 GHz.

### Claim 4 (depends on 3)

The transmitter of claim 3, wherein said balanced power combiner further comprises:
two high-power amplifiers which receive said two power outputs from said phase shifter;
wherein said waveguide hybrid coupler minimizes output losses in said two high-power amplifiers.

### Claim 5 (depends on 4)

The transmitter of claim 4, wherein said SerDes functions up to 3.125 Gsps.

### Claim 6 (depends on 4)

The transmitter of claim 4, wherein a power level of said radio frequency (RF) output can be set within any value within a range of −5 dBm-+3 dBm in 0.5 dB increments, using external universal asynchronous receiver/transmitter (UART) commands.

### Claim 7 (depends on 6)

The transmitter of claim 6, wherein a maximum rate of said OQPSK signal is 1200 Msps, and a maximum 8-PSK symbol rate is 1800 Msps.

### Claim 8 (depends on 7)

The transmitter of claim 7, wherein said synthesizer further includes:
a serializer/deserializer (Ser/Des) clock;
a symbol clock; and
a reference oscillator;
wherein said local oscillator, said serializer/deserializer (Ser/Des) clock, and a clock of at least one of said digital-to-analog converters (DAC), are all coherent with said reference oscillator.

### Claim 9 (depends on 8)

The transmitter of claim 8, wherein said reference oscillator is an oven-controlled crystal oscillator.

### Claim 10 (depends on 8)

The transmitter of claim 8, wherein said SerDes clock 114 has a 100 Hz resolution over a range 100-160 MHz.

### Claim 11 (depends on 8)

The transmitter of claim 8, wherein said filtered I baseband signal and said filtered Q baseband signal received by said second harmonic vector modulator require digital pulse shaping with said plurality of low-pass analog filters, at below said rate of 400 Msps, to meet predetermined spectral mask requirements.

### Claim 12 (depends on 11)

The transmitter of claim 11, wherein said plurality of low-pass analog filters are used exclusively for baseband filtering at rates of 400 Msps and above.

### Claim 13 (depends on 11)

The transmitter of claim 11, wherein said tunable filter bank comprises four low-pass analog filters, and a range of symbol rate is divided into four sub-ranges each assigned to one filter of each of said four low-pass analog filters; and
wherein when a symbol rate is selected, an appropriate one of said four low-pass analog filters is selected by setting control lines of an input and an output radio frequency (RF) single pull 4-throw switches (SS4T).

### Claim 14 (depends on 13)

The transmitter of claim 13, wherein a cutoff frequency of each of said four low-pass analog filters is tunable so that an exact filter cutoff frequency suitable for a given symbol rate can be selected.

### Claim 15 (depends on 14)

The transmitter of claim 14, wherein a plurality of variable capacitance diodes comprises said plurality of low-pass analog filters; and
wherein a tuning of said modulator and the transmitter is accomplished by applying a control voltage to said variable capacitance diodes with said digital-to-analogue converters (DACs).

### Claim 16 (depends on 1)

The transmitter of claim 1, wherein said first modulator can survive a minimum total ionizing dose of 100 kRad-Si, a minimum displacement damage dose of 6.67×108 MeV/g or a 10 MeV equivalent proton fluence of 8.45×1010 cm−2; a 5.50×108 MeV/g or a 10 MeV equivalent proton fluence of 8.35×1010 cm−2, and a single-event latch-up threshold exceeding 37 MeV-cm2/mg.

### Claim 17

A method of providing a high data rate Ka-band modulator and transmitter for space applications, comprising:
receiving data in a data stream into a serializer/deserializer (SerDes) of a field programmable gate array (FPGA) of a first modulator;
buffering said data from said serializer/deserializer (SerDes);
encoding said buffered data in said serial data stream using a low-density parity check (LDPC) encoder with a 7/8 LDPC error-correcting code to result in a data stream of encoded symbols;
randomizing said encoded symbols in said data stream;
splitting said randomized encoded symbols in said serial data stream into an I channel data stream and a Q channel data stream;
digitally filtering each of said I channel data stream and said Q channel data stream, such that rates of said I channel data stream and said Q channel data stream of said encoded symbols below 400 Msps are digitally filtered with a root-raised cosine filter;
parallelizing resulting digitally filtered encoded symbols in said I channel data stream and said Q channel data stream into 12-bit words which are each clocked exiting said FPGA;
receiving said 12-bit words from said FPGA into a plurality of digital-to-analog converters (DACs) to form an I analog baseband signal and a Q analog baseband signal;
filtering said I analog baseband signal and said Q analog baseband signal using a tunable filter bank having a plurality of low-pass analog filters;
receiving said filtered I analog baseband signal and said Q analog baseband signal into a second harmonic vector modulator;
pumping said second harmonic vector modulator using a synthesizer having a local oscillator to output a radio frequency (RF) signal;
wherein said RF signal is an Offset Quadrature Phase Shift Keying (OQPSK) modulated signal at a center frequency equal to: where fIF is a total encoded symbol rate and fLo is a local oscillator frequency; and
wherein said RF signal is in a Ka-band frequency range including inside a Ka-band return link range of 25.25-27.75 GHz.

### Claim 18 (depends on 17)

The method of claim 17, wherein a power level of said radio frequency (RF) output can be set within any value within a range of −5 dBm-+3 dBm in 0.5 dB increments, using external universal asynchronous receiver/transmitter (UART) commands.

### Claim 19 (depends on 18)

The method of claim 18, wherein a maximum rate of said OQPSK signal is 1200 Msps, and a maximum 8-PSK symbol rate is 1800 Msps.

### Claim 20 (depends on 19)

The method of claim 19, wherein said filtered I baseband signal and said filtered Q baseband signal received by said second harmonic vector modulator require digital pulse shaping with said plurality of low-pass analog filters, at below said rate of 400 Msps, to meet predetermined spectral mask requirements; and
wherein said plurality of low-pass analog filters are used exclusively for baseband filtering at rates of 400 Msps and above.