# US 10,374,842 B2 · Equalization for transmitter input buffer array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,842 B2 - Document ID: US10374842B2 - Status: Granted - Kind: B2 - Application number: 16/212,169 - Filed: 2018-12-06 - Published: 2019-06-20 - Granted: 2019-08-06 - Earliest claimed: 2017-09-08 - Assignees: Inphi Corporation - Applicants: Inphi Corporation - Inventors: Karim Abdelhalim; Michael Le; Haidang Lin - Web page: https://patentgrep.com/patent/US10374842B2 ## CPC - H04L 25/0328: {with interference cancellation circuitry (adaptations for interference cancellation within a sequence estimator H04L25/03305; interference related aspects of direct sequence spread spectrum H04B1/7097; interference related aspects of frequency hopping spread spectrum H04B1/715; see also H04B1/10)} - H03K 19/0008: {Arrangements for reducing power consumption} - H04L 2025/03541: {Switching between domains, e.g. between time and frequency} - H04L 2025/03777: {characterised by the signalling} - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract The present invention relates to data communication techniques and integrated circuit devices. More specifically, embodiments of the present invention provide an input buffer module that utilizes one or more equalization elements. The input buffer module includes an array of inverters arranged in a series. An equalization element is configured in series relative to a segment of the array of inverters. The resistance value of the equalization element is predetermined based on a delay associated with the segment of the array of inverters. There are other embodiments as well. ## Claims ### Claim 1 An input buffer device comprising: a first input terminal; a first input slice including a first plurality of inverters that comprises n inverters configured in series, n indicating a first quantity of inverters and being two or greater, the first plurality of inverters including a first inverter and a first group of m inverters, m indicating a second quantity of inverters, the first inverter being coupled to the first input terminal; and a first equalization element characterized by a predetermined resistance value, the predetermined resistance value being based on a delay associated with the first group of m inverters, the first equalization element being configured in series relative to the first group of m inverters. ### Claim 2 (depends on 1) The device of claim 1 wherein the first equalization element comprises a resistor. ### Claim 3 (depends on 1) The device of claim 1 wherein the first equalization element comprises a resistor and a switch. ### Claim 4 (depends on 3) The device of claim 3 wherein the switch disables the first equalization element if a control signal indicates no signals on the first input terminal. ### Claim 5 (depends on 1) The device of claim 1 wherein m is an odd integer. ### Claim 6 (depends on 1) The device of claim 1 wherein the first equalization element comprises an inverter. ### Claim 7 (depends on 1) The device of claim 1 wherein the resistance value is between 500 ohms and 5000 ohms. ### Claim 8 (depends on 1) The device of claim 1 wherein the first input terminal and the second input terminal receive differential input signals. ### Claim 9 (depends on 1) The device of claim 1 further comprising: a first output terminal coupled to the first plurality of inverters; a second input terminal; a second plurality of inverters; a second output terminal coupled to the second plurality of inverters; and a second equalization element coupled to the second plurality of inverters. ### Claim 10 (depends on 1) The device of claim 1 further comprising a second input slice comprising a second plurality of inverters, the second plurality of inverters comprising k number of inverters, k being less than n. ### Claim 11 (depends on 10) The device of claim 10 wherein the first input slice corresponds to an MSB and the second input slice corresponds to an LSB. ### Claim 12 A circuit device comprising: a DAC device configured to convert n bits of input data, n indicating a number of bits; a first input buffer module comprising a first plurality of inverters and a first equalization element, the first input buffer module being configured to provide a first input signal to the DAC device, the first plurality of inverters includes a first a segment of m inverters, m indicating a quantity of inverters, the first segment of m inverters being associated with a first delay value, the first equalization element being characterized by a first predetermined resistance value, the first predetermined resistance value being determined based on the first delay value; and a pre-distortion array coupled to the first input buffer module. ### Claim 13 (depends on 12) The system of claim 12 further comprising a second input buffer module comprising a second plurality of inverters and a second equalization element, the second input buffer module being configured to provide a second input signal to the DAC device, wherein the first input signal and the second input signal form a pair of differential inputs signals. ### Claim 14 (depends on 12) The system of claim 12 wherein each of the n input buffer modules provides a pair of differential input signals. ### Claim 15 (depends on 12) The system of claim 12 wherein m is an odd integer. ### Claim 16 (depends on 12) The system of claim 12 wherein the first equalization element comprises a resistor. ### Claim 17 (depends on 12) The system of claim 12 wherein the first equalization element comprises a transmission gate and a resistor. ### Claim 18 (depends on 13) The system of claim 13 wherein: the second plurality of inverters includes a second a segment of m inverters, the second segment of m inverters being associated with a second delay value; and the second equalization element is characterized by a second predetermined resistance value, the second predetermined resistance value being determined based on the second delay value. ### Claim 19 A data input buffer device comprising: a first input terminal; a first plurality of inverters comprising n inverters configured in series, n indicating a first quantity of inverters and being two or greater, the first plurality of inverters including a first inverter and a first group of m inverters, m indicating a second quantity of inverters, the first inverter being coupled to the first input terminal; a first output terminal coupled to the first plurality of inverters; a second input terminal; a second plurality of inverters comprising n inverters configured in series, the second plurality of inverters including a second inverter and a second group of m inverters, the second inverter being coupled to the second input terminal; a first equalization element being characterized by a first predetermined resistance value, the first predetermined resistance value being based on a delay associated with the second group of m inverters, the first equalization element being configured in series relative to the second group of m inverters; a switch coupled to the first equalization element; and a second output terminal coupled to the second plurality of inverters. ### Claim 20 (depends on 19) The device of claim 19 further comprising a second equalization element being characterized by a second predetermined resistance value, the first predetermined resistance value being based on a delay associated with the first group of m inverters, the second equalization element being configured in series relative to the first group of m inverters.