# US 10,374,793 B2 · Simon-based hashing for fuse validation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,793 B2 - Document ID: US10374793B2 - Status: Granted - Kind: B2 - Application number: 15/374,700 - Filed: 2016-12-09 - Published: 2018-06-14 - Granted: 2019-08-06 - Earliest claimed: 2016-12-09 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Himanshu Kaul; Sanu Mathew; Mark Anders; Jesse Walker; Jason Sandri - Web page: https://patentgrep.com/patent/US10374793B2 ## CPC - H04L 9/0643: {Hash functions, e.g. MD5, SHA, HMAC or f9 MAC} - G06F 12/14: Protection against unauthorised use of memory {or access to memory} - G06F 12/1408: {by using cryptography (for digital transmission H04L9/00)} - G06F 30/00: Computer-aided design [CAD] - G09C 1/00: Apparatus or methods whereby a given sequence of signs, e.g. an intelligible text, is transformed into an unintelligible sequence of signs by transposing the signs or groups of signs or by replacing them by others according to a predetermined system (cryptographic typewriters G09C3/00) - H04L 9/06: the encryption apparatus using shift registers or memories for block-wise {or stream} coding, e.g. DES systems {or RC4; Hash functions; Pseudorandom sequence generators} - H04L 9/0618: {Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation} - H04L 9/0625: {with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI} - G06F 12/0862: with prefetch - G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] - G06F 30/30: Circuit design - G06F 30/333: Design for testability [DFT], e.g. scan chain or built-in self-test [BIST] - G06F 2115/10: Processors - G06F 2117/06: Spare resources, e.g. for permanent fault suppression - G06F 2212/1052: Security improvement - G06F 2212/6026: Prefetching based on access pattern detection, e.g. stride based prefetch - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G09C: CIPHERING OR DECIPHERING APPARATUS FOR CRYPTOGRAPHIC OR OTHER PURPOSES INVOLVING THE NEED FOR SECRECY ## Abstract An instruction and logic for a Simon-based hashing for validation are described. In one embodiment, a processor comprises: a memory the memory to store a plurality of values; and a hash circuit comprising a Simon cipher circuit operable to receive the plurality of values from the memory, to apply a Simon cipher, and to generate an output for each of the plurality of values; and circuitry coupled to the Simon cipher circuit to combine outputs from the Simon cipher circuit for each value of the plurality of values into a hash digest that is indicative of whether the values in the memory are valid. ## Claims ### Claim 1 A processor comprising: a memory to store a plurality of values; and a hash circuit comprising: a Simon cipher circuit operable to apply a Simon cipher to each of the plurality of values and to generate, from and back into a digest register, an output for each of the plurality of values, circuitry coupled to the Simon cipher circuit to combine outputs from the Simon cipher circuit for each value of the plurality of values at each of a plurality of rounds or cycles into the digest register to produce a hash digest that is indicative of whether the values in the memory are valid, wherein the memory comprises a fuse array having a plurality of semiconductor fuses programmed with fuse values, wherein the hash circuit is operable to receive fuse values from the fuse array and generate one or more hashes by applying the Simon cipher to the fuse values. ### Claim 2 (depends on 1) The processor defined in claim 1 wherein the circuitry is operable to generate the hash digest by combining an input to an immediately preceding application of the Simon cipher to one of the plurality of values and an output resulting from the immediately preceding application of the Simon cipher. ### Claim 3 (depends on 2) The processor defined in claim 2 further comprising a controller coupled to the hash circuit and the fuse array to cause the hash circuit to receive the fuse values in the fuse array one at a time and apply the Simon cipher to each of the fuse values separately, until the Simon cipher has been applied to all of the fuse values from the fuse array, the circuitry to combine each output of the Simon cipher when generated with an accumulation from the digest register that is based on previous outputs of the Simon cipher. ### Claim 4 (depends on 1) The processor defined in claim 1 wherein the circuitry implements an XOR gate having: a first XOR gate input coupled to a round logic output of the Simon cipher; a second XOR gate input coupled to an immediately preceding round logic input of the Simon cipher; and an XOR gate output coupled to the round logic input of the Simon cipher. ### Claim 5 (depends on 1) The processor defined in claim 1 further comprising: a fuse microcontroller coupled to the fuse array to provide the fuse values to the hash circuit; wherein the hash circuit comprises a local controller coupled to the fuse microcontroller to request the fuse microcontroller to send the next fuse value from the fuse array only after an immediately preceding hash value provided by the fuse microcontroller has been loaded into the hash circuit. ### Claim 6 (depends on 1) The processor defined in claim 1 wherein the Simon cipher comprises a bit slice datapath for key generation and round logic. ### Claim 7 (depends on 1) The processor defined in claim 1 wherein the hash circuit is bit-serial and includes the Simon cipher circuit, which operates in bit-serial fashion. ### Claim 8 (depends on 1) The processor defined in claim 1 further comprising a microcontroller coupled to the hash circuit via: a first signal interface to indicate to the hash circuit that new data is available for hashing by the hash circuit; a second signal interface for use by the hash circuit to indicate to the microcontroller that the hash circuit has finished applying to Simon cipher with the new data; and a third signal interface to indicate that a hash used in the hash circuit is to be reinitialized when a new data block is started. ### Claim 9 (depends on 8) The processor defined in claim 8 further comprising a local controller to coordinate loading of data into the Simon cipher, wherein the local controller is operable to successively load and internally shift partial data within key storage of the Simon cipher if data loading size is less than key size. ### Claim 10 (depends on 9) The processor defined in claim 9 wherein the local controller uses a linear feedback shift register inside the Simon cipher to track operations in the Simon cipher to determine when to request more input data. ### Claim 11 (depends on 8) The processor defined in claim 8 wherein the hash circuit is operable to receive input data having a prefix prepended to each programmed value and an addend which is padded to make the input data a multiple of the Simon cipher key size used in the hashing circuit. ### Claim 12 A method for fuse value validation, the method comprising: receiving fuse values from a fuse array having a plurality of semiconductor fuses programmed with fuse values; generating one or more hash values by applying a Simon cipher using a hash circuit that receives the fuse values as keys; and generating a value indicative of whether the fuse values in the fuse array are valid based on outputs generated by applying the Simon cipher to each of the fuse values separately, including combining outputs generated by applying the Simon cipher to each of the fuse values into a digest register, wherein the combining comprises combining output of the digest register and output of a Simon cipher circuit through an accumulation circuit and back into the digest register. ### Claim 13 (depends on 12) The method defined in claim 12 wherein generating one or more hash values by applying a Simon cipher to the fuse values using a hash circuit comprises applying the Simon cipher to a first key input that includes one fuse value and a second plaintext input, the second plaintext input being generated by combining an input to an immediately preceding application of the Simon cipher with an output resulting from the immediately preceding application of the Simon cipher. ### Claim 14 (depends on 12) The method defined in claim 12 further comprising generating one or more control signals to obtain fuse values from the fuse array to be sent to the hash circuit one at a time and applying the Simon cipher to each of the fuse values with the second plaintext input until the Simon cipher has been applied to all of the fuse values from the fuse array. ### Claim 15 A system comprising: an interconnect; a dynamic random access memory (DRAM) coupled to the interconnect; and a processor coupled to the interconnect, including a fuse array the fuse array comprising a plurality of semiconductor fuses with fuse values, a hash circuit coupled to the fuse array comprising a Simon cipher circuit operable to receive fuse values from the fuse array and to generate, from and back into a digest register, one or more hashes by applying a Simon cipher to each of the fuse values; and circuitry coupled to the Simon cipher circuit to combine outputs from the Simon cipher circuit for each value of the plurality of values at each of a plurality of rounds or cycles into the digest register to produce a hash digest that is indicative of whether the fuse values in the fuse array are valid. ### Claim 16 (depends on 15) The system defined in claim 15 wherein the circuitry is operable to generate the hash digest by combining an input to an immediately preceding application of the Simon cipher to one of the plurality of values and an output resulting from the immediately preceding application of the Simon cipher. ### Claim 17 (depends on 16) The system defined in claim 16 further comprising a controller coupled to the hash circuit and the fuse array to cause the hash circuit to receive the fuse values in the fuse array one at a time and apply the Simon cipher to each of the fuse values separately, until the Simon cipher has been applied to all of the fuse values from the fuse array, the circuitry to combine each output of the Simon cipher when generated with an accumulation from the digest register that is based on previous outputs of the Simon cipher. ### Claim 18 A tangible, non-transitory, machine-readable medium having stored thereon an instruction, which if performed by a machine causes the machine to perform a method for fuse value validation, the method comprising: receiving fuse values from a fuse array having a plurality of semiconductor fuses programmed with fuse values; generating one or more hash values by applying a Simon cipher using a hash circuit that receives the fuse values as keys; and generating a value indicative of whether the fuse values in the fuse array are valid based on outputs generated by applying the Simon cipher to each of the fuse values separately, including combining outputs generated by applying the Simon cipher to each of the fuse values into a digest register, wherein the combining comprises combining output of the digest register and output of a Simon cipher circuit through an accumulation circuit and back into the digest register. ### Claim 19 (depends on 18) The machine-readable medium defined in claim 18 wherein the method further comprises generating one or more hash values by applying a Simon cipher to the fuse values using a hash circuit comprises applying the Simon cipher to a first key input that includes one fuse value and a second plaintext input, the second plaintext input being generated by combining an input to an immediately preceding application of the Simon cipher with an output resulting from the immediately preceding application of the Simon cipher.