# US 10,374,787 B2 · High performance phase locked loop

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- Number: US 10,374,787 B2
- Document ID: US10374787B2
- Status: Granted
- Kind: B2
- Application number: 16/107,822
- Filed: 2018-08-21
- Published: 2019-01-03
- Granted: 2019-08-06
- Earliest claimed: 2016-04-22
- Assignees: Kandou Labs, S.A.
- Applicants: Kandou Labs, S.A.
- Inventors: Armin Tajalli
- Web page: https://patentgrep.com/patent/US10374787B2

## CPC

- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps}
- H03K 3/356: Bistable circuits
- H03K 5/26: the characteristic being duration, interval, position, frequency, or sequence
- H03L 7/00: Automatic control of frequency or phase; Synchronisation
- H03L 7/0996: {Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator}
- H03L 7/0998: {using phase interpolation}
- H03L 7/104: {using an additional signal from outside the loop for setting or controlling a parameter in the loop (H03L7/107, H03L7/12 take precedence)}
- H04L 7/0012: {by comparing receiver clock with transmitter clock}
- H04L 7/0025: {interpolation of clock signal}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.

## Claims

### Claim 1

A method comprising:
obtaining a plurality of phases of a reference signal and a plurality of phases of a local oscillator signal;
forming at least two partial phase-error signals, each partial phase-error signal formed by:
generating a variable-duty-cycle waveform based on an exclusive OR (XOR) phase comparison between a phase of the reference signal and a phase of the local oscillator signal, wherein a duty cycle of the variable-duty cycle waveform is indicative of a phase error between the phase of the reference signal and the phase of the local oscillator signal; and
providing the variable-duty-cycle waveform to a respective charge pump as a charge pump control signal to generate the partial phase-error signal;
performing a summation of the plurality of partial phase-error signals by injecting or removing charge from a capacitive element according to the plurality of partial phase-error signals to generate a composite phase-error signal; and
providing the composite phase-error signal to a local oscillator generating the plurality of phases of the local oscillator signal.

### Claim 2 (depends on 1)

The method of claim 1, wherein the plurality of phases of the reference signal comprises M phases and wherein the plurality of phases of the local oscillator signal comprises N phases, and wherein the at least two partial phase-error signals comprises M=N partial phase-error signals.

### Claim 3 (depends on 1)

The method of claim 1, wherein the plurality of phases of the reference signal comprises M phases and wherein the plurality of phases of the local oscillator signal comprises N phases, and wherein the at least two partial phase-error signals comprises M×N partial phase-error signals.

### Claim 4 (depends on 1)

The method of claim 1, further comprising applying a weighting factor to each partial phase-error signal of the at least two partial phase-error signals.

### Claim 5 (depends on 4)

The method of claim 4, wherein at least two partial phase-error signals have different weighting factors.

### Claim 6 (depends on 1)

The method of claim 1, wherein the phases of the local oscillator signal are obtained via a phase interpolator.

### Claim 7 (depends on 1)

The method of claim 1, further comprising low-pass filtering the composite phase-error signal.

### Claim 8 (depends on 1)

The method of claim 1, wherein the plurality of phases of the reference signal are obtained via a reference clock signal transmitted on a sub-channel of a vector signaling code.

### Claim 9 (depends on 1)

The method of claim 1, wherein the plurality of phases of the reference signal are obtained via data transitions.

### Claim 10 (depends on 9)

The method of claim 9, further comprising detecting the data transitions at outputs of a plurality of multi-input comparators, each multi-input comparator detecting a respective data stream carried by a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors.

### Claim 11

An apparatus comprising:
a multi-phase comparator configured to obtain a plurality of phases of a reference signal and a plurality of phases of a local oscillator signal, the multi-phase comparator comprising:
a plurality of partial phase comparators configured to form at least two partial phase-error signals, each partial phase-error signal formed by generating a variable-duty-cycle waveform based on an exclusive OR phase comparison between a phase of the reference signal and a phase of the local oscillator signal, wherein a duty cycle of the variable-duty cycle waveform is indicative of a phase error between the phase of the reference signal and the phase of the local oscillator signal; and
a plurality of charge pumps configured to receive respective variable-duty-cycle waveforms as a charge pump control signal and to responsively generate the partial phase-error signal; and
a capacitive element configured to generate a composite phase-error signal based on charge injected or removed from the capacitive element according to the plurality of partial phase-error signals; and
a local oscillator configured to receive the composite phase-error signal and to responsively adjust a fixed phase of the local oscillator according to the composite phase-error signal, the local oscillator generating the plurality of phases of the local oscillator signal.

### Claim 12 (depends on 11)

The apparatus of claim 11, wherein the plurality of phases of the reference signal comprises M phases and wherein the plurality of phases of the local oscillator signal comprises N phases, and wherein the at least two partial phase-error signals comprises M=N partial phase-error signals.

### Claim 13 (depends on 11)

The apparatus of claim 11, wherein the plurality of phases of the reference signal comprises M phases and wherein the plurality of phases of the local oscillator signal comprises N phases, and wherein the at least two partial phase-error signals comprises M×N partial phase-error signals.

### Claim 14 (depends on 11)

The apparatus of claim 11, wherein the partial phase comparators comprise weighted XOR gates configured to further apply a weighting factor to each partial phase-error signal of the at least two partial phase-error signals.

### Claim 15 (depends on 14)

The apparatus of claim 14, wherein at least two partial phase-error signals have different weighting factors.

### Claim 16 (depends on 11)

The apparatus of claim 11, wherein the local oscillator further comprises a phase interpolator.

### Claim 17 (depends on 11)

The apparatus of claim 11, further comprising a low-pass filters configured to filter the composite phase-error signal.

### Claim 18 (depends on 11)

The apparatus of claim 11, wherein the plurality of phases of the reference signal are obtained via a reference clock signal transmitted on a sub-channel of a vector signaling code.

### Claim 19 (depends on 11)

The method of claim 11, wherein the plurality of phases of the reference signal are obtained via data transitions in data streams generated by a plurality of multi-input comparators.

### Claim 20 (depends on 19)

The method of claim 19, wherein the plurality of multi-input comparators are configured to detect respective data streams carried by respective sub-channels of a plurality of mutually orthogonal sub-channels.