# US 10,374,654 B2 · Integrated RF front end with stacked transistor switch

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- Number: US 10,374,654 B2
- Document ID: US10374654B2
- Status: Granted
- Kind: B2
- Application number: 15/917,218
- Filed: 2018-03-09
- Published: 2019-03-14
- Granted: 2019-08-06
- Earliest claimed: 2004-06-23
- Assignees: pSemi Corporation
- Applicants: pSemi Corporation
- Inventors: Mark L. Burgener; James S. Cable
- Web page: https://patentgrep.com/patent/US10374654B2

## CPC

- H04B 1/48: in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter {(H04B1/46 takes precedence)}
- H01Q 23/00: Antennas with active circuits or circuit elements integrated within them or attached to them
- H03F 1/0205: {in transistor amplifiers}
- H03F 1/223: {with MOSFET's}
- H03F 1/56: Modifications of input or output impedances, not otherwise provided for
- H03F 1/565: {using inductive elements}
- H03F 3/189: High-frequency amplifiers, e.g. radio frequency amplifiers
- H03F 3/19: with semiconductor devices only
- H03F 3/21: with semiconductor devices only {(H03F3/245 takes precedence)}
- H03F 3/2171: {with field-effect devices (H03F3/2173 - H03F3/2178 take precedence)}
- H03F 3/68: Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics {(power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602)}
- H03G 3/3042: {in modulators, frequency-changers, transmitters or power amplifiers}
- H03G 11/00: Limiting amplitude; Limiting rate of change of amplitude
- H04B 1/0053: {with common antenna for more than one band}
- H04B 1/0475: {with means for limiting noise, interference or distortion (H04B1/0483 takes precedence)}
- H04L 27/04: Modulator circuits; Transmitter circuits
- H10D 89/60: Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H03F 2200/294: the amplifier being a low noise amplifier [LNA]
- H03F 2200/372: Noise reduction and elimination in amplifier
- H03F 2200/387: A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
- H03F 2200/451: the amplifier being a radio frequency amplifier
- H03F 2200/61: the cascode amplifier has more than one common gate stage
- H04B: TRANSMISSION
- H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72)
- H03F: AMPLIFIERS
- H03G: CONTROL OF AMPLIFICATION
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A monolithic integrated circuit (IC), and method of manufacturing same, that includes all RF front end or transceiver elements for a portable communication device, including a power amplifier (PA), a matching, coupling and filtering network, and an antenna switch to couple the conditioned PA signal to an antenna. An output signal sensor senses at least a voltage amplitude of the signal switched by the antenna switch, and signals a PA control circuit to limit PA output power in response to excessive values of sensed output. Stacks of multiple FETs in series to operate as a switching device may be used for implementation of the RF front end, and the method and apparatus of such stacks are claimed as subcombinations. An iClass PA architecture is described that dissipatively terminates unwanted harmonics of the PA output signal. A preferred embodiment of the RF transceiver IC includes two distinct PA circuits, two distinct receive signal amplifier circuits, and a four-way antenna switch to selectably couple a single antenna connection to any one of the four circuits.

## Claims

### Claim 1

A multiple-MOSFET stack circuit for controlling conduction between a drive output node Vdrive and a reference voltage node Vref under control of an input signal applied between an input signal node and Vref, the circuit comprising:
a. a series transistor stack of J MOSFETs MN, N being an integer between 1 and J and J being an integer 2 or greater, each MOSFET MN having a source SN, a gate GN and a drain DN,
b. an input signal node connected to the gate G1 of a signal-input MOSFET M1 of the MOSFET stack;
c. for 0<N<J, a series coupling between each drain DN and the source S(N+1) of a next higher MOSFET M(N+1) of the MOSFET transistor stack;
d. for 1<N≤J, a gate coupling element that is predominately capacitive connected directly between each gate GN and Vref, wherein, for 1<N≤J, each MOSFET MN is biased to avoid exceeding breakdown characteristics of the FET MN; and where each gate GN is provided with a suitable bias voltage, and wherein the bias voltage is decoupled to Vref;
e. a source coupling for the FET stack between S1 and Vref; and
f. a drain coupling for the FET stack between DJ and Vdrive;
wherein both RF and DC voltages are divided across the transistor stack, and wherein each MOSFET M2 to MN has associated and corresponding bias voltages VB2 to VBN, wherein the bias voltages VB2 to VBN may be individually selected to adjust the DC voltage divided across each corresponding and associated MOSFET M2 to MN, and wherein the divided DC voltage across each MOSFET M2 to MN may be controlled by the bias voltages VB2 to VBN to be identical, or they may be controlled by the bias voltages to be any desired divided DC voltage.

### Claim 2 (depends on 1)

The multiple-MOSFET stack circuit of claim 1, wherein J is an integer 3 or greater.

### Claim 3 (depends on 1)

The multiple-MOSFET stack circuit of claim 1, wherein each MOSFET M2 to MN has associated and corresponding bias resistors RB2 to RBN connected to their associated and corresponding gates of G2 to GN, wherein the bias resistors RB2 to RBN are connected to associated and corresponding bias voltages VB2 to VBN.

### Claim 4 (depends on 1)

The multiple-MOSFET stack circuit of claim 1, wherein each MOSFET M2 to MN has a corresponding and associated gate capacitor CG2 to CGN connected to the gate of each MOSFET M2 to MN, and also connected to a ground reference, and wherein an RF voltage across each MOSFET M2 to MN of the MOSFET transistor stack is determined by values of the associated and corresponding gate capacitors CG2 to CGN.

### Claim 5 (depends on 4)

The multiple-MOSFET stack circuit of claim 4, wherein the DC and RF voltage across any one of the transistors M2 to MN of the transistor stack is controlled by the associated and corresponding bias voltages and gate capacitors, respectively, and wherein the DC and RF voltages divided across any one of the individual MOSFETs M2 to MN of the transistor stack are independently controlled.

### Claim 6 (depends on 4)

The multiple-MOSFET stack circuit of claim 4, wherein the DC voltages across the transistors M2 to MN of the transistor stack are approximately equal.

### Claim 7 (depends on 4)

The multiple-MOSFET stack circuit of claim 4, wherein the RF voltages across the transistors M2 to MN of the transistor stack are approximately equal.

### Claim 8 (depends on 4)

The multiple-MOSFET stack circuit of claim 4, wherein the DC voltages across the transistors M2 to MN of the transistor stack are set to desired values.

### Claim 9 (depends on 4)

The multiple-MOSFET stack circuit of claim 4, wherein the RF voltages across the transistors M2 to MN of the transistor stack are set to desired values.

### Claim 10 (depends on 1)

The multiple-MOSFET stack circuit of claim 1, further comprising an integrated RF Power Amplifier (PA) circuit, the integrated RF PA circuit comprising:
a. an input node that is the input signal node of claim 1; and
b. a matching, coupling and filtering circuit connected to the drive output node.

### Claim 11 (depends on 1)

A Class A, B, C, AB, or F RF PA comprising a circuit according to claim 1, wherein the multiple-MOSFET stack is configured as a primary amplifying device of the Class A, B, or C, AB, or F RF PA.

### Claim 12 (depends on 1)

A quad mixer comprising a circuit according to claim 1.

### Claim 13 (depends on 1)

An RF power management circuit comprising a circuit according to claim 1.