# US 10,374,651 B1 · Systems and methods of relocking for locked loops > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,651 B1 - Document ID: US10374651B1 - Status: Granted - Kind: B1 - Application number: 16/147,658 - Filed: 2018-09-29 - Granted: 2019-08-06 - Earliest claimed: 2018-09-29 - Assignees: QUALCOMM Incorporated - Applicants: Qualcomm Incorporated - Inventors: Shyam Sundar Sivakumar; Kevin Jia-Nong Wang - Web page: https://patentgrep.com/patent/US10374651B1 ## CPC - H03L 7/10: for assuring initial synchronisation or for broadening the capture range - H04B 1/403: using the same oscillator for generating both the transmitter frequency and the receiver local oscillator frequency - H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) - H03L 7/103: {the additional signal being a digital signal} - H03L 7/1075: {by changing characteristics of the loop filter, e.g. changing the gain, changing the bandwidth (H03L7/1072 takes precedence)} - H03L 7/12: using a scanning signal - H04B 1/006: {using switches for selecting the desired band (H04B1/0057 takes precedence)} - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - H04B: TRANSMISSION ## Abstract An apparatus is disclosed for relocking of a locked loop. In an example aspect, the apparatus includes a locked loop, and the locked loop includes a loop and a locked-loop controller that is coupled to the loop. The loop is configured to run responsive to a run signal. The loop includes a memory state component and signal characteristic adjustment circuitry coupled to the memory state component. The signal characteristic adjustment circuitry is configured to produce an output signal having a characteristic that is based on the memory state component. The locked-loop controller is configured to receive an external power mode signal (EPMS). The locked-loop controller is also configured to generate the run signal to have an enable value at a first time when the EPMS is indicative of an external normal mode and at a second time when the EPMS is indicative of an external standby mode. ## Claims ### Claim 1 An apparatus comprising: a locked loop including: a loop configured to run responsive to a run signal, the loop including: a memory state component; and signal characteristic adjustment circuitry coupled to the memory state component, the signal characteristic adjustment circuitry configured to produce an output signal having a characteristic that is based on the memory state component; and a locked-loop controller coupled to the loop, the locked-loop controller configured to: receive an external power mode signal; generate the run signal to have an enable value at a first time when the external power mode signal is indicative of an external normal mode; and generate the run signal to have the enable value at a second time when the external power mode signal is indicative of an external standby mode. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the locked-loop controller is configured, while the external power mode signal is indicative of the external standby mode, to: cause the loop to run to substantially lock to a reference signal at the second time during an external standby mode period; and cause the loop to cease running at a third time during the external standby mode period. ### Claim 3 (depends on 1) The apparatus of claim 1, further comprising: an external power manager configured to: provide the external power mode signal to the locked loop and to a device component separate from the locked loop; and drive the external power mode signal to indicate the external standby mode and the external normal mode. ### Claim 4 (depends on 3) The apparatus of claim 3, wherein the locked-loop controller is configured to generate the run signal to have an enable value responsive to the external power mode signal being changed from the external standby mode to the external normal mode. ### Claim 5 (depends on 3) The apparatus of claim 3, wherein the locked-loop controller is configured to generate the run signal to have a disable value at a third time when the external power mode signal is indicative of the external standby mode. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein: the locked-loop controller includes an internal power manager; the internal power manager includes a timer; and the internal power manager is configured to, responsive to the external power mode signal being indicative of the external standby mode, cycle at least between providing the run signal with the enable value and providing the run signal with the disable value based on the timer. ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the locked-loop controller is configured to override the external power mode signal by enabling the loop to run and update the memory state component during the external standby mode. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein: the memory state component comprises an accumulator that is configured to have a memory state, and the accumulator is configured to store a digital value as the memory state; or the memory state component comprises a capacitor that is configured to have a memory state, and the capacitor is configured to store a voltage differential as the memory state. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the locked loop is configured to gate one or more signals from external circuitry at least during the external standby mode. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein: the locked loop comprises a frequency locked loop (FLL); the output signal has a frequency; and the signal characteristic adjustment circuitry comprises a variable oscillator configured to adjust the frequency of the output signal based on the memory state component. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein: the locked loop comprises a phase locked loop (PLL); the output signal has a phase; and the signal characteristic adjustment circuitry comprises a variable oscillator configured to adjust the phase of the output signal based on the memory state component. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein: the locked loop comprises a delay locked loop (DLL); the output signal is associated with a delay; and the signal characteristic adjustment circuitry comprises a variable delay circuit configured to adjust the delay associated with the output signal based on the memory state component. ### Claim 13 (depends on 1) The apparatus of claim 1, wherein the locked-loop controller includes an internal power manager configured to generate an internal power mode signal, the internal power mode signal indicative of a series of power modes over time including multiple internal pause modes and multiple internal run modes. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the locked-loop controller is configured to enable the loop to run responsive to the external power mode signal being indicative of an external normal mode regardless of a power mode indicated by the internal power mode signal. ### Claim 15 (depends on 13) The apparatus of claim 13, wherein the locked-loop controller is configured to enable the loop to run responsive to the external power mode signal being indicative of the external standby mode and to the internal power mode signal being indicative of an internal run mode of the multiple internal run modes. ### Claim 16 (depends on 13) The apparatus of claim 13, wherein the locked-loop controller is configured to disable the loop from running responsive to the external power mode signal being indicative of the external standby mode and to the internal power mode signal being indicative of an internal pause mode of the multiple internal pause modes. ### Claim 17 (depends on 13) The apparatus of claim 13, wherein each internal run mode of the multiple internal run modes has a duration that is sufficient to enable the loop to substantially lock the output signal to a reference signal after a memory state of the memory state component drifts during an internal pause mode of the multiple internal pause modes. ### Claim 18 (depends on 1) The apparatus of claim 1, wherein the locked-loop controller is configured to cause repetitive current spike events by the locked loop while the external power mode signal is indicative of the external standby mode. ### Claim 19 (depends on 18) The apparatus of claim 18, wherein the loop is configured to exhibit the current spike events as the loop repetitively draws a current with an increased magnitude while running in a feedback mode to repeatedly return the loop to a substantially locked state during the external standby mode. ### Claim 20 (depends on 1) The apparatus of claim 1, wherein the locked-loop controller is configured to keep the loop warm during the external standby mode to reduce a relocking duration that elapses after the external standby mode is terminated relative to a relocking duration for a cold loop. ### Claim 21 (depends on 1) The apparatus of claim 1, further comprising a sensor, wherein: the locked-loop controller includes an internal power manager; and the internal power manager is configured to, responsive to the external power mode signal being indicative of the external standby mode, cycle at least between providing the run signal with the enable value and providing the run signal with a disable value based on information from the sensor. ### Claim 22 A system comprising: a locked loop including: a loop configured to provide an output signal responsive to a run signal; and control means for periodically keeping the loop warm responsive to an external power mode signal being indicative of an external standby mode, the control means configured to provide the run signal to the loop. ### Claim 23 (depends on 22) The system of claim 22, wherein: the system comprises a wireless transceiver; and the locked loop comprises a frequency locked loop (FLL). ### Claim 24 (depends on 22) The system of claim 22, wherein the control means comprises power mode means for establishing for the loop a series of power modes including multiple internal pause modes and multiple internal run modes while the external power mode signal is indicative of the external standby mode. ### Claim 25 (depends on 22) The system of claim 22, wherein the control means is configured to spin up the loop to update the memory state by locking the output signal to a reference signal to account for drift that occurs during a time period in which the external power mode signal is indicative of the external standby mode. ### Claim 26 A method for operating a locked loop, the method comprising: receiving an external power mode signal; responsive to the external power mode signal being indicative of an external normal mode, enabling a loop of the locked loop to run to substantially lock an output signal of the locked loop to a reference signal; and responsive to the external power mode signal being indicative of an external standby mode, disabling the loop of the locked loop from running; and enabling the loop to run toward locking of the output signal to the reference signal. ### Claim 27 (depends on 26) The method of claim 26, wherein: the disabling comprises generating a run signal to have a disable value; the enabling comprises generating the run signal to have an enable value; and the method further comprises switching from the disabling to the enabling based on a trigger. ### Claim 28 (depends on 26) The method of claim 26, further comprising: overriding the external power mode signal being indicative of the external standby mode, the overriding including establishing an internal run mode, wherein the enabling is performed responsive to the establishing of the internal run mode. ### Claim 29 (depends on 26) The method of claim 26, wherein the enabling comprises: running the loop in a feedback mode to adjust a characteristic of the output signal; and updating a memory state of a memory state component to lock the output signal to the reference signal based on the running. ### Claim 30 (depends on 26) The method of claim 26, further comprising: switching from the enabling to the disabling based on at least one of an expiration of a timer or an attainment of a substantially locked state.