# US 10,374,624 B2 · Digital to analog conversion circuit and data source circuit chip

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- Number: US 10,374,624 B2
- Document ID: US10374624B2
- Status: Granted
- Kind: B2
- Application number: 15/305,339
- Filed: 2016-07-12
- Published: 2018-06-21
- Granted: 2019-08-06
- Earliest claimed: 2016-05-26
- Assignees: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Applicants: Shenzhen China Star Optoelectronics Technology Co., Ltd.
- Inventors: Dekang Zeng; Fengcheng Xu; Dongsheng Guo
- Web page: https://patentgrep.com/patent/US10374624B2

## CPC

- H03M 1/66: Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence)
- G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)}
- H03M 1/76: using switching tree
- G09G 2310/027: Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00)

## Abstract

The present disclosure provides a digital to analog conversion (DAC) circuit and a data source circuit chip, the DAC circuit includes: first MOS tubes with the same number of the inputted digital bits; a second resistance, one end of the second resistance connects to the reference voltage, another end of the second resistance connects to the output terminal of the circuit; a second MOS tube, the drain of the second MOS tube connects to the output terminal of the circuit, the gate of the second MOS tube receives a row blank signal; and a capacitor, one end of the capacitor connects to the output terminal, another end of the capacitor is grounded. Using the above circuit and data source circuit chip, can greatly reduce the number of the MOS tube used in the DAC circuit, to effectively reduce the volume of the data source circuit chip and cost.

## Claims

### Claim 1

A digital to analog conversion circuit, the circuit comprises: a plurality of first MOS transistors, wherein a number of the plurality of first MOS transistors is the same with a number with the same number of a plurality of inputted digital bits, wherein, any one of the a gate of any one of the plurality of first MOS transistors receives one of the plurality of digital bits, the any one of the a drain of the any one of the plurality of first MOS transistors connects to an output terminal of the circuit, the any one of the a source of the any one of the plurality of first MOS transistors connects to one end of one of a plurality of first resistance resistors, another end of the one of the plurality of first resistance resistors connects to a reference voltage, a second resistance resistor, one end of the second resistance resistor connects to the reference voltage, another end of the second resistance resistor connects to the output terminal of the circuit, a second MOS transistor, a drain of the second MOS the circuit, a source of the second MOS, transistor is grounded, a gate of the second MOS transistor receives a row blank signal, a capacitor, one end of the capacitor connects to the output terminal of the circuit, another end of the capacitor is grounded, wherein, the any one of the plurality of first MOS transistors is turned on according to a value of the one of the plurality of digital bits received from the gate of the any one of the plurality of first MOS transistors, so that the one of the plurality of first resistors connected to the any one of the plurality of first MOS transistors is connected to the circuit, each of the plurality of first resistors connected to the circuit and the second resistor are parallel connected,
wherein a relationship between a resistance of the parallel connected resistors and a gray voltage of the output terminal of the digital to analog conversion circuit is nonlinear;
wherein, the gray voltage of the output terminal of the digital to analog conversion circuit is calculated by the following:
Vgm=Vref−Vref*e−t/RC
wherein, Vgm is the gray voltage of the output terminal of the digital to analog conversion circuit, Vref is the reference voltage, R is the resistance of the parallel connected resistors, C is a capacitance of the capacitor, t is a charge time of the capacitor.

### Claim 2 (depends on 1)

The circuit according to claim 1, wherein, the capacitance of the capacitor is fixed.

### Claim 3 (depends on 1)

A data source circuit chip, the data source circuit chip comprises a receiver, a shift register, a line memory, a level booster circuit and a digital to analog conversion circuit according to claim 1 and an amplifying circuit.

### Claim 4 (depends on 3)

The data source circuit chip according to claim 3, wherein, the capacitance of the capacitor is fixed.