# US 10,374,622 B2 · System and method for digital-to-analog converter with switched resistor networks

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- Number: US 10,374,622 B2
- Document ID: US10374622B2
- Status: Granted
- Kind: B2
- Application number: 15/986,084
- Filed: 2018-05-22
- Published: 2019-07-11
- Granted: 2019-08-06
- Earliest claimed: 2018-01-05
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Jun Zhang
- Web page: https://patentgrep.com/patent/US10374622B2

## CPC

- H03M 1/0607: {Offset or drift compensation (removal of offset already present on the analogue input signal H03M1/1295)}
- H03M 1/68: with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
- H03M 1/765: {using a single level of switches which are controlled by unary decoded digital signals}
- H03M 1/785: {using resistors, i.e. R-2R ladders}
- H03M 1/808: {using resistors}
- H03M 7/16: Conversion to or from unit-distance codes, e.g. Gray code, reflected binary code
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

## Claims

### Claim 1

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter comprising:
a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits;
a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits; and
a third switched resistor network coupled to the first switched resistor network and to the second switched resistor network, the third switched resistor network having a third configuration, wherein the third configuration is different than the first configuration and different than the second configuration.

### Claim 2 (depends on 1)

The converter of claim 1, wherein the third switched resistor network is for converting a third input differential signal into a third analog output in response to a third set of bits in the plurality of bits.

### Claim 3 (depends on 1)

The converter of claim 1 wherein the first switched resistor network comprises:
a first node for receiving a first reference voltage;
a second node outputting a first output voltage;
a third node for receiving a second reference voltage;
a fourth node outputting a second output voltage;
a first set of resistors switchably selectable to connect between the first node and the second node;
a second set of resistors switchably selectable to connect between the first node and the second node; and
control circuitry for selecting, at a same time, a first resistor in the first set of resistors and a second resistor in the second set of resistors, in response to the first set of bits.

### Claim 4 (depends on 3)

The converter of claim 3 and further comprising:
a first switch operable to connect the first node directly to the second node;
a second switch operable to connect the third node directly to the fourth node; and
wherein the control circuitry is further for selecting, at a same time, only one of the first switch to connect the first node directly to the second node or the second switch to connect the third node directly to the fourth node and at the same time for switchably connecting a first resistor in the first set of resistors or a second resistor in the second set of resistors, in response to the first set of bits.

### Claim 5 (depends on 3)

The converter of claim 3 wherein the control circuitry is for selecting, at a same time, a first resistor in the first set of resistors and a second resistor in the second set of resistors, in response to the first set of bits, wherein the first resistor and the second resistor have different resistance values.

### Claim 6 (depends on 3)

The converter of claim 3 wherein the first set of bits comprise the most significant bits in the plurality of bits.

### Claim 7 (depends on 3)

The converter of claim 3:
wherein each resistor in the first set of resistors has a different resistance value than all other resistors in the first set of resistors; and
wherein each resistor in the second set of resistors has a different resistance value than all other resistors in the second set of resistors.

### Claim 8 (depends on 3)

The converter of claim 3 wherein the second switched resistor network comprises a resistor ladder network.

### Claim 9 (depends on 8)

The converter of claim 8 wherein the second set of bits comprise intermediate significant bits in the plurality of bits.

### Claim 10 (depends on 8)

The converter of claim 8:
wherein the resistor ladder network comprises a plurality of sub-stages; and
wherein each sub-stage comprises a resistor pair, comprising:
a first resistor having a first terminal connected to a first resistor string node and a second terminal connected to an intermediate node;
a second resistor having a third terminal connected to the intermediate node and a fourth terminal connected to a second resistor string node; and
a first switch for selectably connecting:
in a first switch position, the first resistor string node to an intermediate node of a preceding sub-stage resistor pair and the second resistor string node to a fourth terminal of a second resistor in the preceding sub-stage resistor pair; and
in a second switch position, the first resistor string node to a fourth terminal of a second resistor in the preceding sub-stage resistor pair and the fourth terminal of the second resistor in the sub-stage to an intermediate node of the preceding sub-stage resistor pair.

### Claim 11 (depends on 1)

The converter of claim 1, wherein the third switched resistor netowrk is for converting a third input differential signal into a third analog output in response to a third set of an integer N bits in the plurality of bits, wherein the third switched resistor network comprises:
a first node for receiving a first reference voltage;
a second node for receiving a second reference voltage;
a set of N series connected resistors connected between the first node and the second node;
a set of N−1 resistors connected in parallel to one of the resistors in the set of N series connected resistors;
a single resistor connected in parallel to N−1 of the N series connected resistors; and
a set of N switches, wherein each switch in the set of N switches is operable to connect a voltage at a respective terminal of one of the series connected resistors to an output of the third switched resistor network.

### Claim 12 (depends on 11)

The converter of claim 11 and further comprising a decode circuit for receiving the third set of bits and enabling a single switch in the set of N switches at a time, in response to the third set of bits.

### Claim 13 (depends on 12)

The converter of claim 12 wherein the third set of bits comprises the least significant bits in the plurality of bits.

### Claim 14 (depends on 11)

The converter of claim 11 wherein the third set of bits comprises the least significant bits in the plurality of bits.

### Claim 15 (depends on 1)

The converter of claim 1, wherein the third switched resistor network is for converting a third input differential signal into a third analog output in response to a third set of an integer N bits in the plurality of bits, wherein the third switched resistor network comprises:
an integer number 2N of resistors connected in a series string;
the integer number 2N of transistors, wherein each transistor in the integer number 2N of transistors has:
a first terminal connected to a respective terminal of one of the integer number 2N of resistors; and
a second terminal for selectively enabling a respective transistor to output a voltage from the first terminal connected to a respective terminal of one of the integer number 2N of resistors; and
is connected in a serpentine fashion dividing the series string into a number of sets of resistors corresponding to respective rows of resistors and wherein resistors at non-terminal ends of a one of said rows have a same columnar connection via a respective transistor in the integer number 2N of transistors; and
a serpentine decoder for selectively enabling one of the integer number 2N of transistors at a time.

### Claim 16 (depends on 1)

The converter of claim 1 and further comprising:
a buffer for receiving the analog output voltage and for outputting a corresponding buffer analog output voltage; and
wherein the third switched resistor network is for converting a third input differential signal into a third analog output in response to a third set of bits in the plurality of bits; and
wherein the third switched resistor network further comprises circuitry for providing at least one DC offset signal to the buffer.

### Claim 17 (depends on 16)

The converter of claim 16 wherein the circuitry for providing at least one DC offset signal to the buffer comprises a step circuit connected in series with a resistor divider of the third switched resistor network.

### Claim 18 (depends on 16)

The converter of claim 16 wherein the third switched resistor network further comprises circuitry for providing two differential signals for providing a DC offset signal to the buffer.

### Claim 19 (depends on 18)

The converter of claim 18 wherein the buffer comprises interpolation circuitry for adjusting a DC offset of the buffer in response to the two differential signals.

### Claim 20

A method of converting a digital value to an output voltage in response to a digital value comprising a plurality of bits, the method comprising:
inputting a first set of bits in the plurality of bits and selecting a first set of switched resistances in response thereto by a first switched resistor network having a first configuration and thereby converting a first input differential signal into a first analog output;
inputting a second set of bits in the plurality of bits and selecting a second set of switched resistances in response thereto by a second switched resistor network having a second configuration, different from the first configuration, and thereby converting a second input differential signal into a second analog output; and
inputting a third set of bits in the plurality of bits and selecting a third set of switched resistances in response thereto by a third switched resistor network having a third configuration, wherein the third configuration is different than the first configuration and different than the second configuration.

### Claim 21 (depends on 20)

The method of claim 20 and further comprising converting a third input differential signal into a third analog output.