# US 10,374,620 B2 · Frequency divider circuit and a frequency synthesizer circuit

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- Number: US 10,374,620 B2
- Document ID: US10374620B2
- Status: Granted
- Kind: B2
- Application number: 15/488,202
- Filed: 2017-04-14
- Published: 2017-10-19
- Granted: 2019-08-06
- Earliest claimed: 2016-04-18
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Pandou Xue; Guangtao Feng
- Web page: https://patentgrep.com/patent/US10374620B2

## CPC

- H03L 7/18: using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence)
- H03K 3/356113: {using additional transistors in the input circuit}
- H03K 21/026: {comprising logic circuits}
- H03K 21/10: comprising logic circuits
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A frequency divider circuit and a frequency synthesizer circuit are presented, comprising: first and second flip-flops; a phase inverter, wherein an output electrode of the first flip-flop is connected to an input electrode of the second flip-flop and an output electrode of the phase inverter, an output electrode of the second flip-flop is connected to an input electrode of the phase inverter and an input electrode of the first flip-flop, a control electrode of the phase inverter is connected to a control signal; and a control module, wherein the first flip-flop is connected to a voltage source through the control module, the control module is connected to the control signal and controls the connection between the first flip-flop and the voltage source. When the control signal is a first-mode signal, the first flip-flop is disconnected from the voltage source, providing a functionality of a N-division frequency divider. When both the control signal and an output signal of the second flip-flop are a second-mode signal, a functionality of a N+1-division frequency divider is provided.

## Claims

### Claim 1

A frequency divider circuit, comprising:
a first flip-flop;
a second flip-flop;
a phase inverter, wherein an output electrode of the first flip-flop is electrically connected to each of an input electrode of the second flip-flop, two gate electrodes of the second flip-flop, and an output electrode of the phase inverter, wherein an output electrode of the second flip-flop is electrically connected to each of an input electrode of the phase inverter, two gate electrodes of the phase inverter, and an input electrode of the first flip-flop, and wherein a control electrode of the phase inverter is connected to a control signal; and
a control module, wherein the first flip-flop is connected to a voltage source through the control module, wherein the control module is connected to the control signal and controls the connection between the first flip-flop and the voltage source, and wherein when the control signal is a first-mode signal, the first flip-flop is disconnected from the voltage source, providing a functionality of a N-division frequency divider; when both the control signal and an output signal of the second flip-flop are a second-mode signal, a functionality of a N+1-division frequency divider is provided, wherein N is an integer greater than or equal to 2.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the first flip-flop is a D flip-flop, and a first part of the first flip-flop comprises an Extended True Single-Phase Clock (E-TSPC) circuit.

### Claim 3 (depends on 2)

The circuit of claim 2, wherein a second part and a third part of the first flip-flop both comprise a dynamic D latch with a True Single-Phase Clock (TSPC) circuit.

### Claim 4 (depends on 1)

The circuit of claim 1, wherein the control module comprises:
a first p-type Metal-Oxide-Semiconductor (pMOS) transistor, wherein a gate electrode of the first pMOS transistor is connected to the control signal, a drain electrode of the first pMOS transistor is connected to the first flip-flop, and a source electrode of the first pMOS transistor is connected to the voltage source.

### Claim 5 (depends on 1)

The circuit of claim 1, wherein the phase inverter comprises:
a first n-type Metal-Oxide-Semiconductor (nMOS) transistor;
a second nMOS transistor; and
a second pMOS transistor, wherein a source electrode of the first nMOS transistor is grounded, a drain electrode of the first nMOS transistor is connected to a source electrode of the second nMOS transistor, a gate electrode of the first nMOS transistor is connected a control electrode of the phase inverter, a drain electrode of the second nMOS transistor and a drain electrode of the second pMOS transistor are both connected to an output electrode of the phase inverter, a source electrode of the second pMOS transistor is connected to the voltage source, a gate electrode of the second pMOS transistor and a gate electrode of the second nMOS transistor are both connected to an input electrode of the phase inverter.

### Claim 6 (depends on 1)

The circuit of claim 1, wherein the second flip-flop is a D flip-flop with a TSPC circuit.

### Claim 7 (depends on 1)

The circuit of claim 1, wherein the first-mode signal is 1 and the second-mode signal is 0.

### Claim 8 (depends on 1)

The circuit of claim 1, wherein N is 2.

### Claim 9 (depends on 3)

The circuit of claim 3, wherein the first flip-flop comprises:
a third pMOS transistor; and
a third nMOS transistor, wherein a source electrode of the third nMOS transistor is grounded, a gate electrode of the third nMOS transistor is connected to an input electrode of the first flip-flop, a drain electrode of the third nMOS transistor is connected to a drain electrode of the third pMOS transistor, and both are connected to a first node, a gate electrode of the third pMOS transistor is connected to a timing signal, a source electrode of the third pMOS transistor is connected to a voltage node of the first flip-flop.

### Claim 10 (depends on 9)

The circuit of claim 9, wherein the first flip-flop further comprises:
a fourth nMOS transistor;
a fifth nMOS transistor; and
a fourth pMOS transistor, wherein a source electrode of the fourth nMOS transistor is grounded, a gate electrode of the fourth nMOS transistor is connected to the timing signal, a drain electrode of the fourth nMOS transistor is connected to a source electrode of the fifth nMOS transistor, a gate electrode of the fifth nMOS transistor is connected to the first node, the drain electrode of the fifth nMOS transistor and a drain electrode of the fourth pMOS transistor are both connected to a second node, a gate electrode of the fourth pMOS transistor is connected to the timing signal, a source electrode of the fourth pMOS transistor is connected to the voltage node.

### Claim 11 (depends on 10)

The circuit of claim 10, wherein the first flip-flop further comprises:
a sixth nMOS transistor;
a seventh nMOS transistor; and
a fifth pMOS transistor, wherein a source electrode of the sixth nMOS transistor is grounded, a gate electrode of the sixth nMOS transistor is connected to the timing signal, a drain electrode of the sixth nMOS transistor is connected to a source electrode of the seventh nMOS transistor, a drain electrode of the seventh nMOS transistor and a drain electrode of the fifth pMOS transistor are both connected to an output electrode of the first flip-flop, a gate electrode of the seventh nMOS transistor and a gate electrode of the fifth pMOS transistor are both connected to the second node, a source electrode of the fifth pMOS transistor is connected to the voltage node.

### Claim 12 (depends on 6)

The circuit of claim 6, wherein the second flip-flop further comprises:
an eighth nMOS transistor;
a sixth pMOS transistor; and
a seventh pMOS transistor, wherein a source electrode of the eighth nMOS transistor is grounded, a drain electrode of the eighth nMOS transistor and a drain electrode of the sixth pMOS transistor are both connected to a fourth node, a gate electrode of the eighth nMOS transistor and a gate electrode of the sixth pMOS transistor are both connected to an input electrode of the second D flip-flop, a source electrode of the sixth pMOS transistor is connected to a drain electrode of the seventh pMOS transistor, a source electrode of the seventh pMOS transistor is connected to the voltage source, a gate electrode of the seventh pMOS transistor is connected to the timing signal.

### Claim 13 (depends on 12)

The circuit of claim 12, wherein the second flip-flop further comprises:
a ninth nMOS transistor;
a tenth nMOS transistor; and
an eighth pMOS transistor, wherein a source electrode of the ninth nMOS transistor is grounded, a gate electrode of the ninth nMOS transistor is connected to the timing signal, a drain electrode of the ninth nMOS transistor is connected to a source electrode of the tenth nMOS transistor, a gate electrode of the tenth nMOS transistor is connected to the fourth node, a drain electrode of the tenth nMOS transistor and a drain electrode of the eighth pMOS transistor are both connected to a fifth node, a gate electrode of the eighth pMOS transistor is connected to the timing signal, a source electrode of the eighth pMOS transistor is connected to the voltage source.

### Claim 14 (depends on 13)

The circuit of claim 13, wherein the second flip-flop further comprises:
an eleventh nMOS transistor;
a twelfth nMOS transistor; and
a ninth pMOS transistor, wherein a source electrode of the eleventh nMOS transistor is grounded, a gate electrode of the eleventh nMOS transistor is connected to the timing signal, a drain electrode of the eleventh nMOS transistor is connected to a source electrode of the twelfth nMOS transistor, a gate electrode of the twelfth nMOS transistor and a gate electrode of the ninth pMOS transistor are both connected to the fifth node, a drain electrode of the twelfth nMOS transistor and a drain electrode of the ninth pMOS transistor are both connected to a sixth node, a source electrode of a ninth pMOS transistor is connected to the voltage source.

### Claim 15 (depends on 14)

The circuit of claim 14, wherein the second flip-flop further comprises:
a thirteenth nMOS transistor; and
a tenth pMOS transistor, wherein a gate electrode of the thirteenth nMOS transistor and a gate electrode of the tenth pMOS transistor are both connected to the sixth node, a source electrode of the thirteenth nMOS transistor is grounded, a drain electrode of the thirteenth nMOS transistor and a drain electrode of the tenth pMOS transistor are both connected to an output electrode of the second flip-flop, a source electrode of the tenth pMOS transistor is connected to the voltage source.

### Claim 16

A frequency synthesizer circuit, comprising:
a frequency divider circuit, wherein the frequency divider circuit comprises:
a first flip-flop;
a second flip-flop;
a phase inverter, wherein an output electrode of the first flip-flop is electrically connected to each of an input electrode of the second flip-flop, two gate electrodes of the second flip-flop, and an output electrode of the phase inverter, wherein an output electrode of the second flip-flop is electrically connected to each of an input electrode of the phase inverter, two gate electrodes of the phase inverter, and an input electrode of the first flip-flop, and wherein a control electrode of the phase inverter is connected to a control signal; and
a control module, wherein the first flip-flop is connected to a voltage source through the control module, wherein the control module is connected to the control signal and controls the connection between the first flip-flop and the voltage source, and wherein when the control signal is a first-mode signal, the first flip-flop is disconnected from the voltage source, providing a functionality of a N-division frequency divider; when both the control signal and an output signal of the second flip-flop are a second-mode signal, a functionality of a N+1-division frequency divider is provided, wherein N is an integer greater than or equal to 2.

### Claim 17 (depends on 16)

The circuit of claim 16, wherein the first flip-flop is a D flip-flop, and a first part of the first flip-flop comprises an Extended True Single-Phase Clock (E-TSPC) circuit.

### Claim 18 (depends on 17)

The circuit of claim 17, wherein a second part and a third part of the first flip-flop both comprise a dynamic D latch with a True Single-Phase Clock (TSPC) circuit.

### Claim 19 (depends on 16)

The circuit of claim 16, wherein the control module comprises:
a first pMOS transistor, wherein a gate electrode of the first pMOS transistor is connected to the control signal, the drain electrode of the first pMOS transistor is connected to the first flip-flop, a source electrode of the first pMOS transistor is connected to the voltage source.

### Claim 20 (depends on 16)

The circuit of claim 16, wherein the phase inverter comprises:
a first nMOS transistor;
a second nMOS transistor; and
a second pMOS transistor, wherein a source electrode of the first nMOS transistor is grounded, a drain electrode of the first nMOS transistor is connected to a source electrode of the second nMOS transistor, a gate electrode of the first nMOS transistor is connected to a control electrode of the phase inverter, a drain electrode of the second nMOS transistor and a drain electrode of the second pMOS transistor are both connected to an output electrode of the phase inverter, a source electrode of the second pMOS transistor is connected to the voltage source, a gate electrode of the second pMOS transistor and a gate electrode of the second nMOS transistor are both connected to an input electrode of the phase inverter.