# US 10,374,617 B2 · Injection-locked digital bang-bang phase-locked loop with timing calibration

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- Number: US 10,374,617 B2
- Document ID: US10374617B2
- Status: Granted
- Kind: B2
- Application number: 15/693,257
- Filed: 2017-08-31
- Published: 2019-02-21
- Granted: 2019-08-06
- Earliest claimed: 2017-08-15
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Ting-Kuei Kuan; Chin-Yang Wu; Ruey-Bin Sheen; Chih-Hsien Chang
- Web page: https://patentgrep.com/patent/US10374617B2

## CPC

- H03L 7/089: the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence)
- H03L 7/083: the reference signal being additionally directly applied to the generator
- H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence)
- H03L 7/099: concerning mainly the controlled oscillator of the loop
- H03L 7/0992: {comprising a counter or a frequency divider}
- H03L 7/24: using a reference signal directly applied to the generator
- H03L 2207/06: Phase locked loops with a controlled oscillator having at least two frequency control terminals
- H03L 2207/50: All digital phase-locked loop
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)

## Abstract

A phase-locked loop circuit is disclosed. The circuit includes a digital bang-bang phase-locked loop (PLL) electrically connected to an input clock signal connection and an output clock signal connection, and a down-sampling circuit connected to the input clock signal connection. The circuit also includes a digitally-controlled delay line receiving an output of the down-sampling circuit, and an injection pulser receiving an output of the digitally-controlled delay line and connected to provide an injection pulse to a portion of the digital bang-bang phase-locked loop (PLL). The circuit further includes an injection timing calibration circuit connected to a control input of the digitally-controlled delay line. The circuit provides calibration of injection timing and bandwidth optimization, thereby reducing jitter in an output signal from the PLL.

## Claims

### Claim 1

A phase-locked loop (PLL) circuit comprising:
a phase-locked loop (PLL) electrically connected to an input clock signal connection and an output clock signal connection;
a down-sampling circuit connected to the input clock signal connection;
a digitally-controlled delay line receiving an output of the down-sampling circuit;
an injection pulser receiving an output of the digitally-controlled delay line and connected to provide an injection pulse to a portion of the phase-locked loop (PLL); and
an injection timing calibration circuit connected to a control input of the digitally-controlled delay line.

### Claim 2 (depends on 1)

The PLL circuit of claim 1, wherein the phase-locked loop includes:
a bang-bang phase frequency detector;
a digital loop filter connected to a signal output of the bang-bang phase frequency detector;
a digitally controlled oscillator receiving an output signal of the digital loop filter and the injection pulse from the injection pulser, the digitally controlled oscillator configured to output a resulting clock signal at the output clock signal connection; and
a divider providing a signal feedback from an output of the digitally controlled oscillator to the bang-bang phase frequency detector.

### Claim 3 (depends on 2)

The PLL circuit of claim 2, further comprising a bandwidth optimization circuit connected to the signal output of the bang-bang phase frequency detector.

### Claim 4 (depends on 3)

The PLL circuit of claim 3, wherein the bandwidth optimization circuit includes a plurality of flip flop stages connected in series and, for each of the plurality of flip flop stages, a multiplier connected to the output of the corresponding flip flop stage and the signal output of the bang-bang phase frequency detector.

### Claim 5 (depends on 3)

The PLL circuit of claim 3, wherein the bandwidth optimization circuit further includes an integrator connected to outputs of the one bit multipliers, wherein the bandwidth optimization circuit includes at least one output electrically connected to the digital loop filter and the injection timing calibration circuit.

### Claim 6 (depends on 2)

The PLL circuit of claim 2, wherein the injection timing calibration circuit is connected to the signal output of the bang-bang phase frequency detector.

### Claim 7 (depends on 1)

The PLL circuit of claim 1, wherein the down-sampling circuit is configured to down-sample the input clock signal according to a predetermined constant, wherein the predetermined constant is greater than 1.

### Claim 8 (depends on 1)

The PLL circuit of claim 1, wherein the phase-locked loop comprises a digital bang-bang phase-locked loop.

### Claim 9

A method of reducing jitter in a phase-locked loop, the method comprising:
receiving a clock signal at a phase-locked loop and a down-sampling circuit;
based on a sign of the clock signal captured by a phase frequency detector included in the phase-locked loop, calibrating an injection signal timing and enabling output of the down-sampling circuit;
providing an injection signal to a digitally-controlled oscillator included in the phase-locked loop based at least in part on output of an injection pulser receiving an output of a digitally-controlled delay line, the digitally controlled delay line controlled by the calibrated injection signal timing to apply a variable delay to an output from the down-sampling circuit; and
outputting a clock signal from the digitally-controlled oscillator based at least in part on the output signal received from the injection pulser.

### Claim 10 (depends on 9)

The method of claim 9, wherein outputting the clock signal from the digitally-controlled oscillator is further based on an output of a digital line filter connected between the phase frequency detector and the digitally-controlled oscillator.

### Claim 11 (depends on 9)

The method of claim 9, further comprising adjusting operation of the digital line filter via a bandwidth optimization circuit.

### Claim 12 (depends on 9)

The method of claim 9, further comprising providing an injection signal from a divider connected to a control input of the phase frequency detector.

### Claim 13

An injection-locked digital bang-bang phase-locked loop (PLL) circuit comprising:
a digital bang-bang phase-locked loop (PLL) electrically connected to an input clock signal connection and an output clock signal connection, the digital bang-bang PLL comprising:
a bang-bang phase frequency detector;
a digital loop filter connected to a signal output of the bang-bang phase frequency detector;
a digitally controlled oscillator receiving an output signal of the digital loop filter, the digitally controlled oscillator configured to output a resulting clock signal at the output clock signal connection; and
a divider providing a signal feedback from an output of the digitally controlled oscillator to the bang-bang phase frequency detector;
a down-sampling circuit connected to the input clock signal connection;
a digitally-controlled delay line receiving an output of the down-sampling circuit;
an injection pulser receiving an output of the digitally-controlled delay line and connected to provide an injection pulse to the digitally controlled oscillator;
an injection timing calibration circuit connected to a control input of the digitally-controlled delay line; and
a bandwidth optimization circuit connected to the signal output of the bang-bang phase frequency detector and having a control output connected to the digital loop filter.

### Claim 14 (depends on 13)

The injection-locked digital bang-bang phase-locked loop (PLL) circuit of claim 13, wherein the bandwidth optimization circuit includes a plurality of flip flop stages connected in series and, for each of the plurality of flip flop stages, a multiplier connected to the output of the corresponding flip flop stage and the signal output of the bang-bang phase frequency detector.

### Claim 15 (depends on 13)

The injection-locked digital bang-bang phase-locked loop (PLL) circuit of claim 13, wherein the down-sampling circuit is configured to down-sample the input clock signal according to a predetermined constant, wherein the predetermined constant is greater than 1.

### Claim 16 (depends on 13)

The injection-locked digital bang-bang phase-locked loop (PLL) circuit of claim 13, wherein the divider is configured to provide an injection signal to a control input of the bang-bang phase frequency detector.

### Claim 17 (depends on 13)

The injection-locked digital bang-bang phase-locked loop (PLL) circuit of claim 13, wherein the injection timing calibration circuit is connected to the signal output of the bang-bang phase frequency detector.

### Claim 18 (depends on 13)

The injection-locked digital bang-bang phase-locked loop (PLL) circuit of claim 13, further comprising a lock detector connected to the signal output of the bang-bang phase frequency detector.

### Claim 19 (depends on 18)

The injection-locked digital bang-bang phase-locked loop (PLL) circuit of claim 18, wherein the lock detector is configured to output an enable signal to the down-sampling circuit and the injection timing calibration circuit.

### Claim 20 (depends on 13)

The injection-locked digital bang-bang phase-locked loop (PLL) circuit of claim 13, wherein the bandwidth optimization circuit selectively controls the digital line filter and the injection timing calibration circuit based at least in part on the signal output of the bang-bang phase frequency detector.