# US 10,374,616 B2 · Phase frequency detector

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- Number: US 10,374,616 B2
- Document ID: US10374616B2
- Status: Granted
- Kind: B2
- Application number: 15/991,584
- Filed: 2018-05-29
- Published: 2018-12-27
- Granted: 2019-08-06
- Earliest claimed: 2012-09-14
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Wenyan Vivian Jia; Shenggao Li; Fulvio Spagna
- Web page: https://patentgrep.com/patent/US10374616B2

## CPC

- H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00)
- H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop
- G04F 10/005: {Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60)}
- H03D 13/00: Circuits for comparing the phase or frequency of two mutually-independent oscillations {(measuring phase G01R25/00; phase-discriminators with yes/no output G01R25/005)}
- H03L 7/089: the phase or frequency detector generating up-down pulses (H03L7/087 takes precedence)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- G04F: TIME-INTERVAL MEASURING (measuring pulse characteristics G01R, e.g. G01R29/02; in radar or like systems G01S)
- H03D: DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER (masers, lasers H01S; circuits capable of acting both as modulator and demodulator H03C; details applicable to both modulators and frequency-changers H03C; demodulating pulses H03K9/00; transforming types of pulse modulation H03K11/00; coding, decoding or code conversion, in general H03M; repeater stations H04B7/14; demodulators adapted for AC systems of digital information transmission H04L27/00; synchronous demodulators adapted for colour television H04N9/66)

## Abstract

Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

## Claims

### Claim 1

An apparatus comprising:
a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference by expressing higher ordered bits of a digital code that specifies a phase difference; and
a second PFD to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference by expressing a lower ordered bit adjustment to the digital code.

### Claim 2 (depends on 1)

The apparatus of claim 1 further comprising an adder to sum the first and second outputs to generate the digital code.

### Claim 3 (depends on 1)

The apparatus claim 1, wherein the first PFD is to provide a substantially linear characteristic over a wide phase difference of the first clock signal and the second clock signal.

### Claim 4 (depends on 1)

The apparatus of claim 1, wherein the first and second PFDs operate in parallel.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the first and second PFDs operate sequentially.

### Claim 6 (depends on 1)

The apparatus of claim 1, wherein the first PFD is a time-to-digital converter (TDC).

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the second PFD is a bang-bang PFD (BBPFD).

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein the BBPFD comprises a first stage to detect edges of the first and second clock signals, the first stage to generate a phase difference between the first and second clock signals.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the BBPFD comprises a second stage, coupled to the first stage, to sense a fine difference between edges of the first and second clock signals.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein the second stage comprises a sense amplifier based detection circuit.

### Claim 11 (depends on 9)

The apparatus of claim 9, wherein the BBPFD comprises a third stage, coupled to the second stage, to latch an output of the second stage.

### Claim 12 (depends on 1)

The apparatus of claim 1, wherein the first and second PFDs and the adder are part of a PFD of a phase locked loop (PLL) or a delay locked loop (DLL).

### Claim 13 (depends on 12)

The apparatus of claim 12, wherein the PLL is a digital PLL.

### Claim 14 (depends on 1)

The apparatus of claim 1, wherein the first signal is a reference clock signal and the second signal is a feedback clock signal.

### Claim 15

A phase frequency detector (PFD) comprising:
a time-to-digital converter (TDC) to determine a coarse phase difference between a reference clock signal and a feedback clock signal, the TDC to generate a first output indicating the coarse phase difference by expressing higher ordered bits of a digital code that specifies a phase difference;
a bang-bang PFD (BBPFD) to determine a fine phase difference between the reference clock signal and the feedback clock signal, the BBPFD to generate a second output indicating the fine phase difference by expressing a lower ordered bit adjustment to the digital code.

### Claim 16 (depends on 15)

The PFD of claim 15 further comprising an adder to sum the first and second outputs to generate the digital code.

### Claim 17 (depends on 15)

The PFD of claim 15, wherein the TDC is to provide a substantially linear transfer function over a period of the reference clock signal.

### Claim 18

A system comprising:
a memory;
a processor, coupled to the memory, the processor including:
a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference by expressing higher ordered bits of a digital code that specifies a phase difference; and
a second PFD to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference by expressing a lower ordered bit adjustment to the digital code; and
a wireless interface for communicatively coupling the processor to another device.

### Claim 19 (depends on 18)

The system of claim 18, wherein the processor further comprises an adder to sum the first and second outputs to generate the digital code.