# US 10,374,615 B2 · Transmission circuit and integrated circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,615 B2 - Document ID: US10374615B2 - Status: Granted - Kind: B2 - Application number: 15/899,556 - Filed: 2018-02-20 - Published: 2018-08-30 - Granted: 2019-08-06 - Earliest claimed: 2017-02-24 - Assignees: Socionext Inc. - Applicants: Socionext Inc. - Inventors: Taro Moriai - Web page: https://patentgrep.com/patent/US10374615B2 ## CPC - H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) - G06F 11/1004: {to protect a block of data words, e.g. CRC or checksum (G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00)} - H03L 7/087: using at least two phase detectors or a frequency and phase detector in the loop - H04J 3/047: {Distributors with transistors or integrated circuits} - H04J 3/0685: {Clock or time synchronisation in a node; Intranode synchronisation} - H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines} - H04L 7/0091: {Transmitter details} - H04L 7/10: Arrangements for initial synchronisation - G06F 2213/0038: System on Chip - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A transmission circuit includes: a clock generating circuit configured to generate a first clock signal and a second clock signal whose frequency is lower than a frequency of the first clock signal; a first conversion circuit configured to convert, based on the second clock signal, input data into intermediate data whose bit width is narrower than a bit width of the input data; a second conversion circuit configured to convert, based on the first clock signal, the intermediate data into output data whose bit width is narrower than the bit width of the intermediate data; capture circuits configured to sequentially capture a data sequence of the output data; an analysis circuit configured to perform an analysis on the captured data sequence; and a phase adjusting circuit configured to adjust a phase of the second clock signal based on a result of the analysis. ## Claims ### Claim 1 A transmission circuit, comprising: a clock generating circuit configured to generate a first clock signal and a second clock signal whose frequency is lower than a frequency of the first clock signal; a first conversion circuit configured to convert, based on the second clock signal, input data into intermediate data whose bit width is narrower than a bit width of the input data; a second conversion circuit configured to convert, based on the first clock signal, the intermediate data into output data whose bit width is narrower than the bit width of the intermediate data; capture circuits configured to sequentially capture a data sequence of the output data; a detecting circuit configured to detect an edge number or a pulse width of the captured data sequence; and a phase adjusting circuit configured to adjust a phase of the second clock signal based on the detected edge number or pulse width. ### Claim 2 (depends on 1) The transmission circuit according to claim 1, wherein: the detecting circuit is configured to detect the edge number of the captured data sequence; and the phase adjusting circuit is configured to adjust the phase of the second clock signal based on the detected edge number. ### Claim 3 (depends on 1) The transmission circuit according to claim 1, wherein: the detecting circuit is configured to detect the pulse width of the captured data sequence; and the phase adjusting circuit is configured to adjust the phase of the second clock signal based on the detected pulse width. ### Claim 4 (depends on 1) The transmission circuit according to claim 1, wherein the capture circuits are configured to perform the capturing at a plurality of different timings within 1 UI of the data sequence of the output data. ### Claim 5 (depends on 1) The transmission circuit according to claim 1, further comprising selectors configured to select transmission data or test data and output the selected data to the first conversion circuit as the input data, wherein the phase adjusting circuit is configured to adjust the phase of the second clock signal when the selectors select the test data. ### Claim 6 The transmission circuit according to claim wherein: the detecting circuit is configured to detect the edge number or the pulse width of the captured data sequence in a phase range corresponding to one cycle of the second clock signal; and the phase adjusting circuit is configured to adjust the phase of the second clock signal so that the phase of the second clock is in the middle of a normal phase range in which the detected edge number or pulse width being normal. ### Claim 7 (depends on 2) The transmission circuit according to claim 2, wherein the phase adjusting circuit is configured to adjust the phase of the second clock signal so that the detected edge number becomes equal to or less than a threshold value. ### Claim 8 (depends on 3) The transmission circuit according to claim 3, wherein the phase adjusting circuit is configured to adjust the phase of the second clock signal so that the detected pulse width becomes wider than a threshold value. ### Claim 9 An integrated circuit, comprising: an internal circuit configured to generate internal data; and a transmission circuit configured to receive the internal data, wherein the transmission circuit includes: a clock generating circuit configured to generate a first clock signal and a second clock signal whose frequency is lower than a frequency of the first clock signal; a first conversion circuit configured to convert, base d on the second clock signal, input data into intermediate data whose bit width is narrower than a bit width of the input data; a second conversion circuit configured to convert, based on the first clock signal, the intermediate data into output data whose bit width is narrower than the bit width of the intermediate data; capture circuits configured to sequentially capture a data sequence of, the output data; a detecting circuit configured to detect an edge number or a pulse width of the captured data sequence; and a phase adjusting circuit configured to adjust a phase of the second clock signal based on the detected edge number or pulse width. ### Claim 10 (depends on 9) The integrated circuit according to claim 9, wherein the detecting circuit is configured to detect the edge number of the captured data sequence; and the phase adjusting circuit is configured to adjust the phase of the second clock signal based on the detected edge number. ### Claim 11 (depends on 9) The integrated circuit according to claim 9, wherein: the detecting circuit is configured to detect the pulse width of the captured data sequence; and the phase adjusting circuit is configured to adjust the phase of the second clock signal based on the detected pulse width. ### Claim 12 (depends on 9) The integrated circuit according to claim 9, wherein the capture circuits are configured to perform the capturing at a plurality of different timings within 1 UI of the data sequence of the output data. ### Claim 13 (depends on 9) The integrated circuit according to claim 9, wherein: the transmission circuit further includes selectors configured to select transmission data or test data and output the selected data to the first conversion circuit as the input data; and the phase adjusting circuit is configured to adjust the phase of the second clock signal when the selectors select the test data. ### Claim 14 (depends on 9) The integrated circuit according to claim 9, wherein: the detecting circuit is configured to detect the edge number or the pulse width of the captured data sequence in a phase range corresponding to one cycle of the second clock signal; and the phase adjusting circuit is configured to adjust the phase of the second clock signal so that the phase of the second clock signal is in the middle of a normal phase range in which the detected edge number or pulse width being normal. ### Claim 15 (depends on 10) The integrated circuit according to claim 10, wherein the phase adjusting circuit is configured to adjust the phase of the second clock signal so that the detected edge number becomes equal to or less than a threshold value. ### Claim 16 (depends on 11) The integrated circuit according to claim 11, wherein the phase adjusting circuit is configured to adjust the phase of the second clock signal so that the detected pulse width becomes wider than a threshold value.