# US 10,374,614 B2 · Phase and frequency digital synchronizer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,374,614 B2 - Document ID: US10374614B2 - Status: Granted - Kind: B2 - Application number: 15/854,624 - Filed: 2017-12-26 - Published: 2019-06-27 - Granted: 2019-08-06 - Earliest claimed: 2017-12-26 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Gerhard Schrom; Sarath Makala; Kowshik Gandham; Chun Lee - Web page: https://patentgrep.com/patent/US10374614B2 ## CPC - H03L 7/00: Automatic control of frequency or phase; Synchronisation - G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom - G06F 1/12: Synchronisation of different clock signals {provided by a plurality of clock generators} - G06F 1/26: Power supply means, e.g. regulation thereof (for memories G11C) - H03L 7/085: concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) - H03L 7/093: using special filtering or amplification characteristics in the loop (H03L7/087 - H03L7/091 take precedence) - H03L 7/0991: {the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider (H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814)} - H03L 2207/50: All digital phase-locked loop - H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Some embodiments include apparatuses and methods using the apparatuses. Some of the apparatuses include a phase frequency detector to generate output information having a value based on a relationship between a first clock signal and a second clock signal, a memory element to store the values of the output information, a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information, and circuitry to generate the control information based on conditions determined at least from the values stored in the memory element. ## Claims ### Claim 1 An apparatus comprising: a phase frequency detector to generate output information having a value based on a relationship between a first clock signal and a second clock signal; a memory element to store the values of the output information; a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information; and circuitry to generate the control information based on conditions determined at least from the values stored in the memory element, wherein the circuitry is to generate correction information based on a current value of the output information and a previous value of the output information, the circuitry is to adjust a value of the digital code based on the correction information, and the circuitry is to increase a value of the correction information based on a condition determined from the current value of the output information and at least one of previous values of the output information. ### Claim 2 An apparatus comprising: a phase frequency detector to generate output information having a value based on a relationship between a first clock signal and a second clock signal; a memory element to store the values of the output information; a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information; and circuitry to generate the control information based on conditions determined at least from the values stored in the memory element, wherein the circuitry is to generate correction information based on a current value of the output information and a previous value of the output information, the circuitry is to adjust a value of the digital code based on the correction information, and the circuitry is to increase a value of the correction information if the current value of the output information and at least one of previous values of the output information have a same value. ### Claim 3 An apparatus comprising: a phase frequency detector to generate output information having a value based on a relationship between a first clock signal and a second clock signal; a memory element to store the values of the output information; a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information; and circuitry to generate the control information based on conditions determined at least from the values stored in the memory element, wherein the circuitry is to generate correction information based on a current value of the output information and a previous value of the output information, the circuitry is to adjust a value of the digital code based on the correction information, and the circuitry is to decrease a value of the correction information based on a condition determined from the current value of the output information and at least one of previous values of the output information. ### Claim 4 An apparatus comprising: a phase frequency detector to generate output information having a value based on a relationship between a first clock signal and a second clock signal; a memory element to store the values of the output information; a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information; and circuitry to generate the control information based on conditions determined at least from the values stored in the memory element, wherein the circuitry is to generate correction information based on a current value of the output information and a previous value of the output information, the circuitry is to adjust a value of the digital code based on the correction information, and, wherein the circuitry is to decrease a value of the correction information if the current value of the output information and at least one of previous values of the output information have different values. ### Claim 5 An apparatus comprising: a phase frequency detector to generate output information having a value based on a relationship between a first clock signal and a second clock signal; a memory element to store the values of the output information; a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information; and circuitry to generate the control information based on conditions determined at least from the values stored in the memory element, wherein the circuitry is to compute values for proportional control rate information and integral control rate information before decoding the values to generate additional values for calculating the value of the digital code. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the circuitry is to generate correction information based on a current value of the output information and a previous value of the output information, and the circuitry is to adjust a value of the digital code based on the correction information. ### Claim 7 (depends on 5) The apparatus of claim 5, wherein the output information includes a single bit. ### Claim 8 (depends on 7) The apparatus of claim 7, wherein the correction information includes multiple bits. ### Claim 9 An apparatus comprising: a pulse-width modulator (PWM) included in a voltage controller to generate a PWM signal; and a synchronizer included in the voltage controller to generate an output clock signal and provide the output clock signal to the pulse-width modulator as part of generation of the PWM signal, the synchronizer including: a phase frequency detector to generate output information based on a relationship between a first clock signal and a second clock signal; a digital controlled oscillator to generate the second clock signal; circuitry to generate a digital code based on correction information to control the phase and frequency of the second clock signal, the correction information being generated based on a condition determined from at least a first value and second value of the output information, the first value being generated based on a first relationship between the first and second clock signals, the second value being generated based on a second relationship between the first and second clock signals. ### Claim 10 (depends on 9) The apparatus of claim 9, wherein the correction information is generated based on a condition determined from a third value of the output information, the third value being generated based on a third relationship between the first and second clock signals. ### Claim 11 (depends on 9) The apparatus of claim 9, wherein the correction information is generated based on a condition determined from a fourth value of the output information, the fourth value being generated based on a fourth relationship between the first and second clock signals. ### Claim 12 (depends on 9) The apparatus of claim 9, wherein the first relationship between the first and second clock signals is based on timing of an edge of the first clock signal and an edge of the second clock signal. ### Claim 13 (depends on 9) The apparatus of claim 9, wherein the circuitry includes a controller to store the first value and second value of the output information. ### Claim 14 (depends on 9) The apparatus of claim 9, wherein the circuitry includes a log-rate counter to provide the correction information. ### Claim 15 (depends on 9) The apparatus of claim 9, wherein the circuitry is to compute values for proportional control rate information and integral control rate information, and the digital code is generated based on the proportional control rate information and integral control rate information. ### Claim 16 (depends on 9) The apparatus of claim 9, wherein the pulse-width modulator includes a generator to receive the second clock signal from the digital controlled oscillator and generate a triangular wave signal, and the PWM signal is generated based on the triangular wave signal. ### Claim 17 An apparatus comprising: an antenna; and an integrated circuit device coupled to the antenna, the integrated circuit device including a voltage regulator, the voltage regulator including a pulse-width modulator, the pulse-width modulator including a frequency synchronizer, the frequency synchronizer including: a phase frequency detector to generate output information at an output of the phase frequency detector, the output information having a value based on a relationship between a first clock signal and a second clock signal; a memory element to store the values of the output information; a digital control oscillator to generate the second clock signal having a phase and frequency based on a digital code, the digital code having a value based on control information; and circuitry to generate the control information based on conditions determined at least from the values stored in the memory element. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the integrated circuit device includes a processor. ### Claim 19 (depends on 17) The apparatus of claim 17, further comprising a connector coupled to the integrated circuit device, the connector conforming with at least one of Universal Serial Bus (USB), DisplayPort (DP), High-Definition Multimedia Interface (HDMI), Thunderbolt, Ethernet, and Peripheral Component Interconnect Express (PCIe) specifications.